LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 343

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
Table 306. USB Device Interrupt Priority register (USBDevIntPri - address 0xFFE0 C22C) bit description
Table 307. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xFFE0 C230) bit allocation
Reset value: 0x0000 0000
UM10237_4
User manual
Bit
0
1
7:2
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
FRAME
EP_FAST
-
9.3.6 USB Device Interrupt Priority register (USBDevIntPri - 0xFFE0 C22C)
9.4.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0xFFE0 C230)
EP15TX
EP11TX
EP7TX
EP3TX
9.4 Endpoint interrupt registers
31
23
15
7
Value
0
1
0
1
-
Writing one to a bit in this register causes the corresponding interrupt to be routed to the
USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the
USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed
to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, no
interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write only register.
The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts are
used in Slave mode operation.
Each physical non-isochronous endpoint is represented by a bit in this register to indicate
that it has generated an interrupt. All non-isochronous OUT endpoints generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet is successfully transmitted, or when a NAK
handshake is sent on the bus and the interrupt on NAK feature is enabled (see
13–11.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page
this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be set
depending on the value of the coreesponding bit of USBEpDevIntPri. USBEpIntSt is a
read only register.
Note that for Isochronous endpoints, handling of packet data is done when the FRAME
interrupt occurs.
EP15RX
EP11RX
EP7RX
EP3RX
30
22
14
FRAME interrupt is routed to USB_INT_REQ_LP.
FRAME interrupt is routed to USB_INT_REQ_HP.
EP_FAST interrupt is routed to USB_INT_REQ_LP.
Reserved, user software should not write ones to reserved bits. The value
6
Description
EP_FAST interrupt is routed to USB_INT_REQ_HP.
read from a reserved bit is not defined.
EP14TX
EP10TX
EP6TX
EP2TX
29
21
13
5
Rev. 04 — 26 August 2009
EP14RX
EP10RX
EP6RX
EP2RX
28
20
12
4
EP13TX
Chapter 13: LPC24XX USB device controller
EP9TX
EP5TX
EP1TX
27
19
11
3
EP13RX
EP9RX
EP5RX
EP1RX
26
18
10
2
365). A bit set to one in
EP12TX
EP8TX
EP4TX
EP0TX
25
17
UM10237
9
1
© NXP B.V. 2009. All rights reserved.
Reset value
0
0
NA
Section
EP12RX
EP8RX
EP4RX
EP0RX
343 of 792
24
16
8
0