LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 559

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
5.3.8 Data counter
Note: The DPSM remains in the WAIT_S state for at least two clock periods to meet Nwr
timing constraints.
If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the
IDLE state.
If a timeout occurs while the DPSM is in the BUSY state, it sets the data timeout flag and
moves to the IDLE state.
The data timer is enabled when the DPSM is in the WAIT_R or BUSY state, and
generates the data timeout error:
The data counter has two functions:
•
•
•
•
•
•
SEND: The DPSM starts sending data to a card. Depending on the transfer mode bit
in the data control register, the data transfer mode can be either block or stream:
– In block mode, when the data block counter reaches zero, the DPSM sends an
– In stream mode, the DPSM sends data to a card while the enable bit is HIGH and
BUSY: The DPSM waits for the CRC status flag:
– If it does not receive a positive CRC status, it moves to the IDLE state and sets the
– If it receives a positive CRC status, it moves to the WAIT_S state if MCIDAT0 is not
When transmitting data, the timeout occurs if the DPSM stays in the BUSY state for
longer than the programmed timeout period
When receiving data, the timeout occurs if the end of the data is not true, and if the
DPSM stays in the WAIT_R state for longer than the programmed timeout period.
To stop a data transfer when it reaches zero. This is the end of the data condition.
To start transferring a pending command (see
the stop command for a stream data transfer.
internally generated CRC code and end bit, and moves to the BUSY state.
the data counter is not zero. It then moves to the IDLE state.
CRC fail status flag.
LOW (the card is not busy).
Rev. 04 — 26 August 2009
Chapter 21: LPC24XX SD/MMC card interface
Figure
21–110). This is used to send
UM10237
© NXP B.V. 2009. All rights reserved.
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