LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 76

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
Table 67.
UM10237_4
User manual
Address
0xFFE0 8124
0xFFE0 8140
0xFFE0 8144
0xFFE0 8160
0xFFE0 8164
0xFFE0 8200
0xFFE0 8204
0xFFE0 8208
0xFFE0 820C EMCStatic WaitRd0
0xFFE0 8210
0xFFE0 8214
0xFFE0 8218
0xFFE0 8220
0xFFE0 8224
0xFFE0 8228
0xFFE0 822C EMCStatic WaitRd1
0xFFE0 8230
0xFFE0 8234
0xFFE0 8238
0xFFE0 8240
0xFFE0 8244
0xFFE0 8248
0xFFE0 824C EMCStatic WaitRd2
0xFFE0 8250
0xFFE0 8254
0xFFE0 8258
0xFFE0 8260
0xFFE0 8264
Summary of EMC registers
Register Name
EMCDynamic RasCas1
EMCDynamic Config2
EMCDynamic RasCas2
EMCDynamic Config3
EMCDynamic RasCas3
EMCStatic Config0
EMCStatic WaitWen0
EMCStatic WaitOen0
EMCStatic WaitPage0
EMCStatic WaitWr0
EMCStatic WaitTurn0
EMCStatic Config1
EMCStatic WaitWen1
EMCStatic WaitOen1
EMCStatic WaitPage1
EMCStatic WaitWr1
EMCStatic WaitTurn1
EMCStatic Config2
EMCStatic WaitWen2
EMCStatic WaitOen2
EMCStatic WaitPage2
EMCStatic WaitWr2
EMCStatic WaitTurn2
EMCStatic Config3
EMCStatic WaitWen3
…continued
Description
Selects the RAS and CAS latencies for dynamic memory
chip select 1.
Selects the configuration information for dynamic
memory chip select 2.
Selects the RAS and CAS latencies for dynamic memory
chip select 2.
Selects the configuration information for dynamic
memory chip select 3.
Selects the RAS and CAS latencies for dynamic memory
chip select 3.
Selects the memory configuration for static chip select 0. -
Selects the delay from chip select 0 to write enable.
Selects the delay from chip select 0 or address change,
whichever is later, to output enable.
Selects the delay from chip select 0 to a read access.
Selects the delay for asynchronous page mode
sequential accesses for chip select 0.
Selects the delay from chip select 0 to a write access.
Selects the number of bus turnaround cycles for chip
select 0.
Selects the memory configuration for static chip select 1. -
Selects the delay from chip select 1 to write enable.
Selects the delay from chip select 1 or address change,
whichever is later, to output enable.
Selects the delay from chip select 1 to a read access.
Selects the delay for asynchronous page mode
sequential accesses for chip select 1.
Selects the delay from chip select 1 to a write access.
Selects the number of bus turnaround cycles for chip
select 1.
Selects the memory configuration for static chip select 2. -
Selects the delay from chip select 2 to write enable.
Selects the delay from chip select 2 or address change,
whichever is later, to output enable.
Selects the delay from chip select 2 to a read access.
Selects the delay for asynchronous page mode
sequential accesses for chip select 2.
Selects the delay from chip select 2 to a write access.
Selects the number of bus turnaround cycles for chip
select 2.
Selects the memory configuration for static chip select 3. -
Selects the delay from chip select 3 to write enable.
Rev. 04 — 26 August 2009
Chapter 5: LPC24XX External Memory Controller (EMC)
Warm
Reset
Value
[1]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UM10237
© NXP B.V. 2009. All rights reserved.
POR
Reset
Value
[1]
0x303 R/W
0x0
0x303 R/W
0x0
0x303 R/W
0x0
0x0
0x1F
0x1F
0x1F
0xF
0x0
0x0
0x1F
0x1F
0x1F
0xF
0x0
0x0
0x1F
0x1F
0x1F
0xF
0x0
0x0
0x0
0x0
0x0
76 of 792
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W