LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 491

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
8.12 Receive Data Register B (CAN1RDB - 0xE004 402C, CAN2RDB -
8.13 Transmit Frame Information Register (CAN1TFI[1/2/3] - 0xE004 40[30/
Table 431. Receive Data register A (CAN1RDA - address 0xE004 4028, CAN2RDA - address
0xE004 802C)
This register contains the 5th through 8th Data bytes of the current received message. It is
read-only in normal operation, but can be written for testing purposes if the RM bit in
CANMOD is 1. See
Table 432. Receive Data register B (CAN1RDB - address 0xE004 402C, CAN2RDB - address
40/50], CAN2TFI[1/2/3] - 0xE004 80[30/40/50])
When the corresponding TBS bit in CANSR is 1, software can write to one of these
registers to define the format of the next transmit message for that Tx buffer. Bits not listed
read as 0 and should be written as 0.
The values for the reserved bits of the CANxTFI register in the Transmit Buffer should be
set to the values expected in the Receive Buffer for an easy comparison, when using the
Self Reception facility (self test), otherwise they are not defined.
The CAN Controller consist of three Transmit Buffers. Each of them has a length of 4
words and is able to store one complete CAN message as shown in
The buffer layout is subdivided into Descriptor and Data Field where the first word of the
Descriptor Field includes the TX Frame Info that describes the Frame Format, the Data
Length and whether it is a Remote or Data Frame. In addition, a TX Priority register allows
the definition of a certain priority for each transmit message. Depending on the chosen
Frame Format, an 11-bit identifier for Standard Frame Format (SFF) or an 29-bit identifier
for Extended Frame Format (EFF) follows. Note that unused bits in the TID field have to
be defined as 0. The Data Field in TDA and TDB contains up to eight data bytes.
Bit
15:8
23:16 Data 3
31:24 Data 4
Bit
7:0
15:8
23:16 Data 7
31:24 Data 8
Symbol Function
Data 2
Symbol Function
Data 5
Data 6
0xE004 8028) bit description
0xE004 802C) bit description
If the DLC field in CANRFS
of the current received message.
If the DLC field in CANRFS
of the current received message.
If the DLC field in CANRFS
of the current received message.
If the DLC field in CANRFS
of the current received message.
If the DLC field in CANRFS
of the current received message.
If the DLC field in CANRFS
of the current received message.
If the DLC field in CANRFS
of the current received message.
Table 18–417
Rev. 04 — 26 August 2009
for details on specific CAN channel register address.
Chapter 18: LPC24XX CAN controllers CAN1/2
≥
≥
≥
≥
≥
≥
≥
0010, this contains the first Data byte
0100, this contains the first Data byte
0101, this contains the first Data byte
1000, this contains the first Data byte
0011, this contains the first Data byte
0110, this contains the first Data byte
0111, this contains the first Data byte
Figure
UM10237
© NXP B.V. 2009. All rights reserved.
18–74.
Reset
Value
0
0
0
Reset
Value
0
0
0
0
491 of 792
RM
Set
X
X
X
RM
Set
X
X
X
X