LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 89

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
Table 86.
[1]
[2]
Address mappings that are not shown in
Table 87.
Bit
2:0
4:3
6:5
12:7
13
14
18:15 -
19
20
31:21 -
14
16 bit external bus high-performance address mapping (Row, Bank, Column)
0
0
0
0
0
0
The SDRAM column and row width and number of banks are computed automatically from the address
mapping.
The buffers must be disabled during SDRAM and SyncFlash initialization. They must also be disabled when
performing SyncFlash commands. The buffers must be enabled during normal operation.
12
0
0
0
0
0
0
Symbol
-
Memory device
(MD)
-
Address
mapping (AM)
-
Address
mapping (AM)
Buffer enable
(B)
Write protect (P) 0
11:9 8:7
000
000
001
001
010
010
Dynamic Memory Configuration registers (EMCDynamicConfig0-3 - address
0xFFE0 8100, 0xFFE0 8120, 0xFFE0 8140, 0xFFE0 8160) bit description
Address mapping
00
01
00
01
00
01
Description
16 MB (2Mx8), 2 banks, row length = 11, column length = 9
16 MB (1Mx16), 2 banks, row length = 11, column length = 8
64 MB (8Mx8), 4 banks, row length = 12, column length = 9
64 MB (4Mx16), 4 banks, row length = 12, column length = 8
128 MB (16Mx8), 4 banks, row length = 12, column length = 10
128 MB (8Mx16), 4 banks, row length = 12, column length = 9
Rev. 04 — 26 August 2009
-
00
01
10
11
-
0
0
0
1
1
Value Description
-
-
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
SDRAM (POR reset value).
Low-power SDRAM.
Micron SyncFlash.
Reserved.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
See
000000 = reset value.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
See
0 = reset value.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Buffer disabled for accesses to this chip select (POR
reset value).
Buffer enabled for accesses to this chip select.
Writes not protected (POR reset value).
Writes protected.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Table 5–87
Table 5–87
Table 5–87
[1]
are reserved.
UM10237
© NXP B.V. 2009. All rights reserved.
[2]
89 of 792
Reset
Value
NA
00
NA
0
NA
0
NA
0
NA