LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 236

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
7.2.17 Flow Control Status Register (FlowControlStatus - 0xFFE0 0174)
7.3.1 Receive Filter Control Register (RxFilterCtrl - 0xFFE0 0200)
7.3 Receive filter register definitions
Table 221. Flow Control Counter register (FlowControlCounter - address 0xFFE0 0170) bit
The Flow Control Status register (FlowControlStatus) is a Read Only register with an
address of 0xFFE0 8174.
Table 222. Flow Control Status register (FlowControlStatus - address 0xFFE0 8174) bit
The Receive Filter Control register (RxFilterCtrl) has an address of 0xFFE0 0200.
Table 11–223
Table 223. Receive Filter Control register (RxFilterCtrl - address 0xFFE0 0200) bit
Bit
15:0
31:16
Bit
15:0
31:16
Bit
0
1
2
3
4
5
11:6
Symbol
AcceptUnicastEn
AcceptBroadcastEn
AcceptMulticastEn
AcceptUnicastHashEn
AcceptMulticastHashEn
AcceptPerfectEn
-
Symbol
MirrorCounter
PauseTimer
Symbol
MirrorCounterCurrent In full duplex mode this register represents the current
-
description
description
description
lists the definition of the individual bits in the register.
Rev. 04 — 26 August 2009
Table 11–222
Function
In full duplex mode the MirrorCounter specifies the number
of cycles before re-issuing the Pause control frame.
In full-duplex mode the PauseTimer specifies the value
that is inserted into the pause timer field of a pause flow
control frame. In half duplex mode the PauseTimer
specifies the number of backpressure cycles.
Function
value of the datapath’s mirror counter which counts up to
the value specified by the MirrorCounter field in the
FlowControlCounter register. In half duplex mode the
register counts until it reaches the value of the PauseTimer
bits in the FlowControlCounter register.
Unused
When set to ’1’, multicast frames that pass the
Function
When set to ’1’, all unicast frames are accepted.
When set to ’1’, all broadcast frames are accepted.
When set to ’1’, all multicast frames are accepted.
When set to ’1’, unicast frames that pass the imperfect
hash filter are accepted.
imperfect hash filter are accepted.
When set to ’1’, the frames with a destination address
identical to the
station address are accepted.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
lists the bit definitions of the register.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
236 of 792
Reset
value
0
0
0
0
0
0
NA
Reset
value
0x0
0x0
Reset
value
0x0
0x0