LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 155

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
[2]
[3]
[4]
[5]
[6]
[7]
[8]
5. LPC2470/78 pinning information
Table 123. LPC2470/78 pin allocation table
UM10237_4
User manual
Pin Symbol
Row A
1
5
9
13
17
Row B
1
5
9
13
17
Row C
1
5
9
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
Open-drain 5 V tolerant digital I/O pad, compatible with I
functionality. When power is switched off, this pin connected to the I
configuration applies to all functions on this pin.
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
Pad provides special analog functionality.
P3[27]/D27/
CAP1[0]/PWM1[4]
P1[4]/ENET_TX_EN
P1[17]/ENET_MDIO
P3[20]/D20/
PWM0[5]/DSR1
P1[5]/ENET_TX_ER/
MCIPWR/PWM0[3]
P3[2]/D2
P1[1]/ENET_TXD1
P4[25]/WE
V
P2[0]/PWM1[1]/TXD1/
TRACECLK/LCDPWR
P3[13]/D13
P3[9]/D9
V
DD(3V3)
DD(3V3)
Pin Symbol
2
6
10
14
2
6
10
14
2
6
10
P1[3]/ENET_TXD3/
V
P1[9]/ENET_RXD0
MCICMD/PWM0[2]
P1[11]/ENET_RXD2/
MCIDAT2/PWM0[6]
-
P3[10]/D10
V
P4[29]/BLS3/MAT2[1]/
LCDVD[7]/LCDVD[11]/
LCDVD[3]/RXD3
P3[19]/D19/
PWM0[4]/DCD1
-
TDI
P3[22]/D22/
PCAP0[0]/RI1
P3[21]/D21/
PWM0[6]/DTR1
SSIO
SSIO
Rev. 04 — 26 August 2009
2
C-bus 400 kHz specification. It requires an external pull-up to provide output
Pin Symbol
3
7
11
15
3
7
11
15
3
7
11
2
C-bus is floating and does not disturb the I
P1[0]/ENET_TXD0
P1[14]/ENET_RX_ER
P4[15]/A15
P0[8]/I2STX_WS/
LCDVD[16]/MISO1/
MAT2[2]
-
P3[1]/D1
P4[30]/CS0
P1[6]/ENET_TX_CLK/
MCIDAT0/PWM0[4]
P4[14]/A14
-
RTCK
P1[8]/ENET_CRS_DV/
ENET_CRS
P4[28]/BLS2/MAT2[0]/
LCDVD[6]/LCDVD[10]/
LCDVD[2]/TXD3
Chapter 8: LPC24XX Pin configuration
Pin Symbol
4
8
12
16
4
8
12
16
4
8
12
P4[31]/CS1
P1[15]/
ENET_REF_CLK/
ENET_RX_CLK
V
P1[12]/ENET_RXD3/
MCIDAT3/PCAP0[0]
-
P3[0]/D0
P4[24]/OE
P0[4]/I2SRX_CLK/
LCDVD[0]/RD2/CAP2[0]
P4[13]/A13
-
P0[2]/TXD0
P1[10]/ENET_RXD1
P0[5]/I2SRX_WS/
LCDVD[1]/TD2/CAP2[1]
SSIO
UM10237
2
© NXP B.V. 2009. All rights reserved.
C lines. Open-drain
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