LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 528

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
5. SPI peripheral details
UM10237_4
User manual
5.1 General information
5.2 Master operation
When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal
goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is
set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on
the last clock edge where data is sampled.
There are four registers that control the SPI peripheral. They are described in detail in
Section 19–7 “Register description” on page
The SPI control register contains a number of programmable bits used to control the
function of the SPI block. The settings for this register must be set up prior to a given data
transfer taking place.
The SPI status register contains read only bits that are used to monitor the status of the
SPI interface, including normal functions, and exception conditions. The primary purpose
of this register is to detect completion of a data transfer. This is indicated by the SPIF bit.
The remaining bits in the register are exception condition indicators. These exceptions will
be described later in this section.
The SPI data register is used to provide the transmit and receive data bytes. An internal
shift register in the SPI block logic is used for the actual transmission and reception of the
serial data. Data is written to the SPI data register for the transmit case. There is no buffer
between the data register and the internal shift register. A write to the data register goes
directly into the internal shift register. Therefore, data should only be written to this register
when a transmit is not currently in progress. Read data is buffered. When a transfer is
complete, the receive data is transferred to a single byte data buffer, where it is later read.
A read of the SPI data register returns the value of the read data buffer.
The SPI clock counter register controls the clock rate when the SPI block is in master
mode. This needs to be set prior to a transfer taking place, when the SPI block is a
master. This register has no function when the SPI block is a slave.
The I/Os for this implementation of SPI are standard CMOS I/Os. The open drain SPI
option is not implemented in this design. When a device is set up to be a slave, its I/Os are
only active when it is selected by the SSEL signal being active.
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be the master. This process assumes that any prior data transfer
has already completed.
1. Set the SPI clock counter register to the desired clock rate.
2. Set the SPI control register to the desired settings.
3. Write the data to transmitted to the SPI data register. This write starts the SPI data
4. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
transfer.
after the last cycle of the SPI data transfer.
Rev. 04 — 26 August 2009
531.
Chapter 19: LPC24XX SPI
UM10237
© NXP B.V. 2009. All rights reserved.
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