LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 784

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
5
Chapter 17: LPC24XX UART1
1
2
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Chapter 18: LPC24XX CAN controllers CAN1/2
1
2
3
4
4.1
4.2
4.3
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
8
8.1
8.2
8.3
UM10237_4
User manual
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Basic configuration . . . . . . . . . . . . . . . . . . . . 443
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 444
Register description . . . . . . . . . . . . . . . . . . . 444
How to read this chapter . . . . . . . . . . . . . . . . 467
Basic configuration . . . . . . . . . . . . . . . . . . . . 467
CAN controllers . . . . . . . . . . . . . . . . . . . . . . . 467
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 468
CAN controller architecture . . . . . . . . . . . . . 469
Memory map of the CAN block. . . . . . . . . . . 473
Register description . . . . . . . . . . . . . . . . . . . 473
UART1 Receiver Buffer Register (U1RBR -
0xE001 0000, when DLAB = 0 Read Only) . 447
UART1 Transmitter Holding Register (U1THR -
0xE001 0000 when DLAB = 0, Write Only) . 447
UART1 Divisor Latch LSB and MSB Registers
(U1DLL - 0xE001 0000 and U1DLM -
0xE001 0004, when DLAB = 1) . . . . . . . . . . 447
UART1 Interrupt Enable Register (U1IER -
0xE001 0004, when DLAB = 0) . . . . . . . . . . 448
UART1 Interrupt Identification Register (U1IIR -
0xE001 0008, Read Only) . . . . . . . . . . . . . . 449
UART1 FIFO Control Register (U1FCR -
0xE001 0008, Write Only). . . . . . . . . . . . . . . 452
UART1 Line Control Register (U1LCR -
0xE001 000C). . . . . . . . . . . . . . . . . . . . . . . . 452
UART1 Modem Control Register (U1MCR -
0xE001 0010) . . . . . . . . . . . . . . . . . . . . . . . . 453
Auto-flow control . . . . . . . . . . . . . . . . . . . . . . 454
General CAN features . . . . . . . . . . . . . . . . . 468
CAN controller features . . . . . . . . . . . . . . . . 468
Acceptance filter features . . . . . . . . . . . . . . . 468
APB Interface Block (AIB) . . . . . . . . . . . . . . 469
Interface Management Logic (IML). . . . . . . . 469
Transmit Buffers (TXB) . . . . . . . . . . . . . . . . . 470
Receive Buffer (RXB) . . . . . . . . . . . . . . . . . 470
Error Management Logic (EML) . . . . . . . . . 471
Bit Timing Logic (BTL) . . . . . . . . . . . . . . . . . 471
Bit Stream Processor (BSP) . . . . . . . . . . . . . 471
CAN controller self-tests . . . . . . . . . . . . . . . . 471
Global self test . . . . . . . . . . . . . . . . . . . . . . . .472
Local self test . . . . . . . . . . . . . . . . . . . . . . . . .472
Mode Register (CAN1MOD - 0xE004 4000,
CAN2MOD - 0xE004 8000) . . . . . . . . . . . . . 475
Command Register (CAN1CMR - 0xE004 x004,
CAN2CMR - 0xE004 8004) . . . . . . . . . . . . . 476
Global Status Register (CAN1GSR -
0xE004 x008, CAN2GSR - 0xE004 8008) . . 478
RX error counter . . . . . . . . . . . . . . . . . . . . . . .479
Rev. 04 — 26 August 2009
4.9.1
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.17.1
4.17.1.1
4.17.1.2
4.18
5
8.4
8.5
8.6
8.7
8.8
8.9
8.9.1
8.10
8.11
8.12
8.13
Chapter 36: LPC24XX Supplementary information
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
UART1 Line Status Register (U1LSR -
0xE001 0014, Read Only) . . . . . . . . . . . . . . 456
UART1 Modem Status Register (U1MSR -
0xE001 0018). . . . . . . . . . . . . . . . . . . . . . . . 457
UART1 Scratch Pad Register (U1SCR -
0xE001 001C) . . . . . . . . . . . . . . . . . . . . . . . 458
UART1 Auto-baud Control Register (U1ACR -
0xE001 0020). . . . . . . . . . . . . . . . . . . . . . . . 458
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 460
UART1 Fractional Divider Register (U1FDR -
0xE001 0028). . . . . . . . . . . . . . . . . . . . . . . . 461
Baudrate calculation . . . . . . . . . . . . . . . . . . 462
Example 1: PCLK = 14.7456 MHz,
BR = 9600 . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Example 2: PCLK = 12 MHz, BR = 115200 . 464
UART1 Transmit Enable Register (U1TER -
0xE001 0030). . . . . . . . . . . . . . . . . . . . . . . . 464
TX error counter. . . . . . . . . . . . . . . . . . . . . . . 480
Interrupt and Capture Register (CAN1ICR -
0xE004 400C, CAN2ICR - 0xE004 800C) . . 480
Interrupt Enable Register (CAN1IER -
0xE004 4010, CAN2IER - 0xE004 8010). . . 484
Bus Timing Register (CAN1BTR - 0xE004 4014,
CAN2BTR - 0xE004 8014). . . . . . . . . . . . . . 485
Baud rate prescaler . . . . . . . . . . . . . . . . . . . . 486
Synchronization jump width . . . . . . . . . . . . . . 486
Time segment 1 and time segment 2. . . . . . . 486
Error Warning Limit Register (CAN1EWL -
0xE004 4018, CAN2EWL - 0xE004 8018). . 487
Status Register (CAN1SR - 0xE004 401C,
CAN2SR - 0xE004 801C) . . . . . . . . . . . . . . 487
Receive Frame Status Register (CAN1RFS -
0xE004 4020, CAN2RFS - 0xE004 8020) . . 489
ID index field . . . . . . . . . . . . . . . . . . . . . . . . 490
Receive Identifier Register (CAN1RID -
0xE004 4024, CAN2RID - 0xE004 8024) . . 490
Receive Data Register A (CAN1RDA -
0xE004 4028, CAN2RDA - 0xE004 8028) . . 490
Receive Data Register B (CAN1RDB -
0xE004 402C, CAN2RDB - 0xE004 802C) . 491
Transmit Frame Information Register
(CAN1TFI[1/2/3] - 0xE004 40[30/ 40/50],
CAN2TFI[1/2/3] - 0xE004 80[30/40/50]) . . . 491
Automatic transmit priority detection . . . . . . . 492
Tx DLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
UM10237
© NXP B.V. 2009. All rights reserved.
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