LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 741

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
4. Pin description
UM10237_4
User manual
The ARM7TDMI-S core has a Debug Communication Channel function in-built. The
debug communication channel allows a program running on the target to communicate
with the host debugger or another separate host without stopping the program flow or
even entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
Table 677. EmbeddedICE pin description
[1]
[2]
Pin Name
DBGEN
TMS
TCK
TDI
TDO
nTRST
RTCK
•
•
[1]
trigger on an access to a peripheral and the second to trigger on the code segment
that performs the task switching. Therefore when the breakpoints trigger the
information regarding which task has switched out will be ready for examination.
The watchpoints can be configured such that a range of addresses are enabled for
the watchpoints to be active. The RANGE function allows the breakpoints to be
combined such that a breakpoint is to occur if an access occurs in the bottom
256 bytes of memory but not in the bottom 32 bytes.
For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and
Boundary Scan Architecture.
This pin has a built-in pull-up resistor.
This pin has no built-in pull-up and no built-in pull-down resistor.
[2]
[1]
[2]
[1]
[1]
[1]
Type
Input
Input
Input
Input
Output
Input
Output
Rev. 04 — 26 August 2009
Description
Debug Enable . JTAG interface control signal (see
Test Mode Select. The TMS pin selects the next state in the TAP state
machine.
Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It
is a positive edgetriggered clock with the TMS and TCK signals that
define the internal state of the device.
Remark: This clock must be slower than 1 ⁄ 6 of the CPU clock (CCLK) for
the JTAG interface to operate.
Test Data In. This is the serial data input for the shift register.
Test Data Output. This is the serial data output from the shift register.
Data is shifted out of the device on the negative edge of the TCK signal.
Test Reset. The nTRST pin can be used to reset the test logic within the
EmbeddedICE logic.
Returned Test Clock. Extra signal added to the JTAG port. Required for
designs based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization with
targets having slow or widely varying clock frequency. For details refer to
"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)" .
Board designers may need to connect a weak bias resistor to this pin as
described below.
Chapter 33: LPC24XX EmbeddedICE
Section
UM10237
© NXP B.V. 2009. All rights reserved.
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