LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 460

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
4.16 Auto-baud modes
When the software is expecting an ”AT" command, it configures the UART1 with the
expected character format and sets the U1ACR Start bit. The initial values in the divisor
latches U1DLM and U1DLM don‘t care. Because of the ”A" or ”a" ASCII coding
(”A" = 0x41, ”a" = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected
character are delimited by two falling edges. When the U1ACR Start bit is set, the
auto-baud protocol will execute the following phases:
1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the
2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If
6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to
ratemin
UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate.
measuring counter will start counting pclk cycles.
the frequency of the UART1 input clock, guaranteeing the start bit is stored in the
U1RSR.
counter will continue incrementing with the pre-scaled UART1 input clock (pclk).
normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt
U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the
remaining bits of the ”A/a" character.
Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.
=
2 P
------------------------ -
16 2 15
× CLK
×
Rev. 04 — 26 August 2009
≤
UART
1
baudrate
≤
----------------------------------------------------------------------------------------------------------- -
16
×
(
2
+
databits
PCLK
+
Chapter 17: LPC24XX UART1
paritybits
+
UM10237
stopbits
© NXP B.V. 2009. All rights reserved.
)
=
460 of 792
ratemax