LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 785

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
8.14
8.15
8.16
9
9.1
9.2
9.3
9.4
10
10.1
10.2
10.3
11
12
12.1
12.2
12.3
12.4
13
14
15
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
15.10
15.11
15.12
Chapter 19: LPC24XX SPI
1
2
UM10237_4
User manual
CAN controller operation . . . . . . . . . . . . . . . 494
Centralized CAN registers. . . . . . . . . . . . . . . 495
Global acceptance filter . . . . . . . . . . . . . . . . 497
Acceptance filter modes . . . . . . . . . . . . . . . . 497
Sections of the ID look-up table RAM . . . . . 498
ID look-up table RAM. . . . . . . . . . . . . . . . . . . 498
Acceptance filter registers . . . . . . . . . . . . . . 500
Basic configuration . . . . . . . . . . . . . . . . . . . . 526
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Transmit Identifier Register (CAN1TID[1/2/3] -
0xE004 40[34/44/54], CAN2TID[1/2/3] -
0xE004 80[34/44/54]) . . . . . . . . . . . . . . . . . . 493
Transmit Data Register A (CAN1TDA[1/2/3] -
0xE004 40[38/48/58], CAN2TDA[1/2/3] -
0xE004 80[38/48/58]) . . . . . . . . . . . . . . . . . . 493
Transmit Data Register B (CAN1TDB[1/2/3] -
0xE004 40[3C/4C/5C], CAN2TDB[1/2/3] -
0xE004 80[3C/4C/5C]) . . . . . . . . . . . . . . . . . 494
Error handling . . . . . . . . . . . . . . . . . . . . . . . . 494
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . 494
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Transmit priority . . . . . . . . . . . . . . . . . . . . . . 495
Central Transmit Status Register (CANTxSR -
0xE004 0000) . . . . . . . . . . . . . . . . . . . . . . . . 495
Central Receive Status Register (CANRxSR -
0xE004 0004) . . . . . . . . . . . . . . . . . . . . . . . . 496
Central Miscellaneous Status Register (CANMSR
- 0xE004 0008) . . . . . . . . . . . . . . . . . . . . . . . 496
Acceptance filter Off mode . . . . . . . . . . . . . . 497
Acceptance filter Bypass mode . . . . . . . . . . 498
Acceptance filter Operating mode . . . . . . . . 498
FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . 498
Acceptance Filter Mode Register (AFMR -
0xE003 C000). . . . . . . . . . . . . . . . . . . . . . . . 500
Section configuration registers . . . . . . . . . . . 501
Standard Frame Individual Start Address Register
(SFF_sa - 0xE003 C004) . . . . . . . . . . . . . . . 502
Standard Frame Group Start Address Register
(SFF_GRP_sa - 0xE003 C008) . . . . . . . . . . 502
Extended Frame Start Address Register (EFF_sa
- 0xE003 C00C) . . . . . . . . . . . . . . . . . . . . . . 503
Extended Frame Group Start Address Register
(EFF_GRP_sa - 0xE003 C010) . . . . . . . . . . 503
End of AF Tables Register (ENDofTable -
0xE003 C014). . . . . . . . . . . . . . . . . . . . . . . . 504
Status registers . . . . . . . . . . . . . . . . . . . . . . . 504
LUT Error Address Register (LUTerrAd -
0xE003 C018). . . . . . . . . . . . . . . . . . . . . . . . 504
LUT Error Register (LUTerr - 0xE003 C01C) 505
Global FullCANInterrupt Enable register (FCANIE
- 0xE003 C020) . . . . . . . . . . . . . . . . . . . . . . 505
FullCAN Interrupt and Capture registers
(FCANIC0 - 0xE003 C024 and FCANIC1 -
0xE003 C028). . . . . . . . . . . . . . . . . . . . . . . . 505
Rev. 04 — 26 August 2009
16
16.1
17
17.1
17.2
17.2.1
17.2.2
17.2.3
17.2.4
17.2.5
17.2.6
17.3
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
17.3.6
18
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
3
4
Chapter 36: LPC24XX Supplementary information
Configuration and search algorithm . . . . . . 506
FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . . 507
Examples of acceptance filter tables and ID
index values. . . . . . . . . . . . . . . . . . . . . . . . . . 518
SPI overview . . . . . . . . . . . . . . . . . . . . . . . . . 526
SPI data transfers . . . . . . . . . . . . . . . . . . . . . 526
Acceptance filter search algorithm. . . . . . . . 506
FullCAN message layout . . . . . . . . . . . . . . . 509
FullCAN interrupts . . . . . . . . . . . . . . . . . . . . . 511
FullCAN message interrupt enable bit . . . . . . 511
Message lost bit and CAN channel number. 512
Setting the interrupt pending bits
(IntPnd 63 to 0) . . . . . . . . . . . . . . . . . . . . . . 513
Clearing the interrupt pending bits
(IntPnd 63 to 0) . . . . . . . . . . . . . . . . . . . . . . 513
Setting the message lost bit of a FullCAN
message object (MsgLost 63 to 0). . . . . . . . 513
Clearing the message lost bit of a FullCAN
message object (MsgLost 63 to 0). . . . . . . . 513
Set and clear mechanism of the FullCAN
interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Scenario 1: Normal case, no message lost . 513
Scenario 2: Message lost. . . . . . . . . . . . . . . 514
Scenario 3: Message gets overwritten indicated
by Semaphore bits . . . . . . . . . . . . . . . . . . . . 515
Scenario 3.1: Message gets overwritten indicated
by Semaphore bits and Message Lost. . . . . 515
Scenario 3.2: Message gets overwritten indicated
by Message Lost . . . . . . . . . . . . . . . . . . . . . 516
Scenario 4: Clearing Message Lost bit . . . . 517
Example 1: only one section is used . . . . . . 518
Example 2: all sections are used . . . . . . . . . 518
Example 3: more than one but not all sections are
used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Configuration example 4 . . . . . . . . . . . . . . . 519
Configuration example 5 . . . . . . . . . . . . . . . 519
Configuration example 6 . . . . . . . . . . . . . . . 520
Explicit standard frame format identifier section
(11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 521
Group of standard frame format identifier section
(11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 521
Explicit extended frame format identifier section
(29-bit CAN ID,
Group of extended frame format identifier section
(29-bit CAN ID,
Configuration example 7 . . . . . . . . . . . . . . . 522
FullCAN explicit standard frame format identfier
section (11-bit CAN ID) . . . . . . . . . . . . . . . . . 523
Explicit standard frame format identifier section
(11-bit CAN ID) . . . . . . . . . . . . . . . . . . . . . . . 523
FullCAN message object data section . . . . . . 523
Look-up table programming guidelines . . . . 524
Figure
Figure
18–92) . . . . . . . . . . . . 521
18–92) . . . . . . . . . . . . 521
UM10237
© NXP B.V. 2009. All rights reserved.
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