LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 727
LPC2468FBD208,551
Manufacturer Part Number
LPC2468FBD208,551
Description
IC ARM7 MCU FLASH 512K 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4261
935282457551
LPC2468FBD208-S
935282457551
LPC2468FBD208-S
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UM10237_4
User manual
6.2.1 Channel Source Address Registers (DMACC0SrcAddr - 0xFFE0 4100 and
6.2.2 Channel Destination Address Registers (DMACC0DestAddr - 0xFFE0 4104
6.2 Channel registers
The channel registers are used to program the two DMA channels. These registers
consist of:
When performing scatter/gather DMA the first four registers are automatically updated.
DMACC1SrcAddr - 0xFFE0 4120)
The two read/write DMACCxSrcAddr Registers contain the current source address
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the appropriate channel is enabled. When the DMA channel is enabled
this register is updated:
Reading the register when the channel is active does not provide useful information. This
is because by the time software has processed the value read, the channel might have
progressed. It is intended to be read only when the channel has stopped, in which case it
shows the source address of the last item read.
Note: The source and destination addresses must be aligned to the source and
destination widths.
Table 32–667
Table 667. Channel Source Address registers (DMACC0SrcAddr - address 0xFFE0 4100 and
and DMACC1DestAddr - 0xFFE0 4124)
The two read/write DMACCxDestAddr Registers contain the current destination address
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the channel is enabled. When the DMA channel is enabled the register is
updated as the destination address is incremented and by following the linked list when a
complete packet of data has been transferred. Reading the register when the channel is
active does not provide useful information. This is because by the time that software has
processed the value read, the channel might have progressed. It is intended to be read
only when a channel has stopped, in which case it shows the destination address of the
last item read.
Register.
Bit
31:0
•
•
•
•
•
•
•
Two DMACCxSrcAddr Registers
Two DMACCxDestAddr Registers
Two DMACCxLLI Registers
Two DMACCxControl Registers
Two DMACCxConfiguration Registers
As the source address is incremented.
By following the linked list when a complete packet of data has been transferred.
Symbol
SrcAddr
DMACC1SrcAddr - address 0xFFE0 4120) bit description
shows the bit assignments of the DMACCxSrcAddr Registers.
Table 32–668
Description
DMA source address.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
shows the bit assignments of the DMACCxDestAddr
UM10237
© NXP B.V. 2009. All rights reserved.
0x0000 0000
Reset Value
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