LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 225

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
Table 195. Test register (TEST - address 0xFFE0 ) bit description
Table 196. MII Mgmt Configuration register (MCFG - address 0xFFE0 0020) bit description
Table 197. Clock select encoding
UM10237_4
User manual
Bit
0
1
2
31:3
Bit
0
1
4:2
14:5
15
31:16
Clock Select
Host Clock divided by 4
Host Clock divided by 6
Host Clock divided by 8
Host Clock divided by 10
Host Clock divided by 14
Host Clock divided by 20
Host Clock divided by 28
Symbol
SHORTCUT PAUSE
QUANTA
TEST PAUSE
TEST
BACKPRESSURE
-
Symbol
SCAN INCREMENT
SUPPRESS
PREAMBLE
CLOCK SELECT
-
RESET MII MGMT
-
7.1.10 MII Mgmt Command Register (MCMD - 0xFFE0 0024)
7.1.9 MII Mgmt Configuration Register (MCFG - 0xFFE0 0020)
The MII Mgmt Configuration register (MCFG) has an address of 0xFFE0 0020. The bit
definition of this register is shown in
The MII Mgmt Command register (MCMD) has an address of 0xFFE0 0024. The bit
definition of this register is shown in
Function
This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.
This bit causes the MAC Control sublayer to inhibit transmissions, just as if a
PAUSE Receive Control frame with a nonzero pause time parameter was received.
Setting this bit will cause the MAC to assert backpressure on the link. Backpressure
causes preamble to be transmitted, raising carrier sense. A transmit packet from the
system will be sent during backpressure.
Unused
Function
Set this bit to cause the MII Management hardware to perform read cycles across a
range of PHYs. When set, the MII Management hardware will perform read cycles
from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow
continuous reads of the same PHY.
Set this bit to cause the MII Management hardware to perform read/write cycles
without the 32 bit preamble field. Clear this bit to cause normal cycles to be
performed. Some PHYs support suppressed preamble.
This field is used by the clock divide logic in creating the MII Management Clock
(MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs
support clock rates up to 12.5 MHz, however. Refer to
definition of values for this field.
Unused
This bit resets the MII Management hardware.
Unused
Rev. 04 — 26 August 2009
Table
Table
11–196.
11–198.
Bit 4
0
0
0
1
1
1
1
Table 11–197
Chapter 11: LPC24XX Ethernet
Bit 3
0
1
1
0
0
1
1
below for the
UM10237
© NXP B.V. 2009. All rights reserved.
Bit 2
x
0
1
0
1
0
1
225 of 792
Reset
value
0
0
0
0x0
Reset
value
0
0
0
0x0
0
0x0