LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 720

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
6. Register description
UM10237_4
User manual
5.9 Programming a DMA channel
To program a DMA channel:
The GPDMA registers are shown in
Table 652. Summary of GPDMA registers
Name
General Registers
DMACIntStatus
DMACIntTCStatus
DMACIntTCClear
DMACIntErrorStatus
DMACIntErrClr
DMACRawIntTCStatus
DMACRawIntErrorStatus Raw Error Interrupt Status
1. Choose a free DMA channel with the priority required. DMA channel 0 has the highest
2. Clear any pending interrupts on the channel to be used by writing to the
3. Write the source address into the DMACCxSrcAddr Register
4. Write the destination address into the DMACCxDestAddr Register
5. Write the address of the next Linked List Item (LLI) into the DMACCxLLI Register
6. Write the control information into the DMACCxControl Register
7. Write the channel configuration information into the DMACCxConfiguration Register
priority and DMA channel 1 the lowest priority.
DMACIntTCClr Register
(DMACIntClear - 0xFFE0
“Interrupt Error Clear Register (DMACIntErrClr - 0xFFE0
channel operation might have left interrupts active.
“Channel Source Address Registers (DMACC0SrcAddr - 0xFFE0 4100 and
DMACC1SrcAddr - 0xFFE0
“Channel Destination Address Registers (DMACC0DestAddr - 0xFFE0 4104 and
DMACC1DestAddr - 0xFFE0
(Section 32–6.2.3 “Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108
and DMACC1LLI - 0xFFE0
then 0 must be written into this register.
“Channel Control Registers (DMACC0Control - 0xFFE0 410C and DMACC0Control -
0xFFE0
(Section 32–6.2.6 “Channel Configuration Registers (DMACC0Configuration -
0xFFE0 4110 and DMACC1Configuration - 0xFFE0
then the DMA channel is automatically enabled.
412C)”).
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Description
Interrupt Status Register
Interrupt Terminal Count
Status Register
Interrupt Terminal Count Clear
Register
Interrupt Error Status Register RO
Interrupt Error Clear Register
Raw Interrupt Terminal Count
Status Register
Register
(Section 32–6.1.3 “Interrupt Terminal Count Clear Register
4008)”) and DMACIntErrClr Register
4128)”). If the transfer consists of a single packet of data
4120)”).
4124)”).
Table
32–652.
Access Reset
RO
RO
WO
WO
RO
RO
4130)”). If the Enable bit is set
4010)”). The previous
Value
0x0
0x0
-
0x0
-
-
-
(Section 32–6.2.1
(Section 32–6.1.5
[1]
(Section 32–6.2.4
UM10237
(Section 32–6.2.2
© NXP B.V. 2009. All rights reserved.
Address
0xFFE0 4000
0xFFE0 4004
0xFFE0 4008
0xFFE0 400C
0xFFE0 4010
0xFFE0 4014
0xFFE0 4018
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