LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 57

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
3.3.1 CPU Clock Configuration register (CCLKCFG - 0xE01F C104)
3.3 Clock dividers
It's very important not to merge any steps above. For example, don't update the PLLCFG
and enable the PLL simultaneously with the same feed sequence.
The output of the PLL must be divided down for use by the CPU and the USB block.
Separate dividers are provided such that the CPU frequency can be determined
independently from the USB block, which always requires 48 MHz with a 50% duty cycle
for proper operation (see
The CCLKCFG register controls the division of the PLL output before it is used by the
CPU. When the PLL is bypassed, the division may be by 1. When the PLL is running, the
output must be divided in order to bring the CPU clock frequency (cclk) within operating
limits. An 8 bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off the PLL.
Note: When the USB interface is used in an application, cclk must be at least 18 MHz in
order to support internal operations of the USB block.
Table 53.
The cclk is derived from the PLL output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 1 results in CCLK being one half the PLL output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL output, etc..
Bit Symbol
7:0 CCLKSEL
6. Enable the PLL with one feed sequence.
7. Change the CPU Clock Divider setting for the operation with the PLL. It's critical to do
8. Wait for the PLL to achieve lock by monitoring the PLOCK bit in the PLLSTAT register,
9. Connect the PLL with one feed sequence.
this before connecting the PLL.
or using the PLOCK interrupt, or wait for a fixed time when the input clock to PLL is
slow (i.e. 32 kHz). The value of PLOCK may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
frequency divided by the pre-divider value) is less than 100 kHz or greater than
20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF
seconds when FREF is less than 400 kHz.
CPU Clock Configuration register (CCLKCFG - address 0xE01F C104) bit
description
Description
Selects the divide value for creating the CPU clock (CCLK) from the
PLL output.
Only 0 and odd values (1, 3, 5, ..., 255) are supported and can be
used when programming the CCLKSEL bits.
Warning: Using an even value (2, 4, 6, ..., 254) when setting the
CCLKSEL bits may result in incorrect operation of the device.
Rev. 04 — 26 August 2009
Figure
4–12).
Chapter 4: LPC24XX Clocking and power control
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
value
0x00
57 of 792