LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 315
LPC2468FBD208,551
Manufacturer Part Number
LPC2468FBD208,551
Description
IC ARM7 MCU FLASH 512K 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4261
935282457551
LPC2468FBD208-S
935282457551
LPC2468FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2468FBD208,551
Manufacturer:
TI
Quantity:
1 908
Company:
Part Number:
LPC2468FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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UM10237_4
User manual
7.12 Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028)
7.11 Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024)
The LCD_INTSTAT register is Read-Only, and contains a bit-by-bit logical AND of the
LCD_INTRAW register and the LCD_INTMASK register. A logical OR of all interrupts is
provided to the system interrupt controller.
The contents of LCD_INTSTAT register are described in
Table 270. Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024)
The LCD_INTCLR register is Write-Only. Writing a logic 1 to the relevant bit clears the
corresponding interrupt.
The contents of the LCD_INTCLR register are described in
Table 271. Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028)
Bits
31:5
4
3
2
1
0
Bits
31:5
4
3
Function
reserved
BERMIS
VCompMIS
LNBUMIS
FUFMIS
reserved
Function
reserved
BERIC
VCompIC
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
AHB master bus error masked interrupt status.
Set when the both the BERRAW bit in the LCD_INTRAW
register and the BERIM bit in the LCD_INTMSK register are set.
Vertical compare masked interrupt status.
Set when the both the VCompRIS bit in the LCD_INTRAW
register and the VCompIM bit in the LCD_INTMSK register are
set.
LCD next address base update masked interrupt status.
Set when the both the LNBURIS bit in the LCD_INTRAW
register and the LNBUIM bit in the LCD_INTMSK register are
set.
FIFO underflow masked interrupt status.
Set when the both the FUFRIS bit in the LCD_INTRAW register
and the FUFIM bit in the LCD_INTMSK register are set.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
AHB master error interrupt clear.
Writing a 1 to this bit clears the AHB master error interrupt.
Vertical compare interrupt clear.
Writing a 1 to this bit clears the vertical compare interrupt.
Chapter 12: LPC24XX LCD controller
Table
Table
12–270.
12–271.
UM10237
© NXP B.V. 2009. All rights reserved.
315 of 792
Reset
value
-
0x0
0x0
0x0
0x0
-
Reset
value
-
0x0
0x0
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