LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 264

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
9.8 Transmission retry
9.9 Status hash CRC calculations
Each pair of nibbles transferred on the MII interface (or four pairs of bits for RMII) is
transferred as a byte on the data write interface after being delayed by 128 or 136 cycles
for filtering by the receive filter and buffer modules. The Ethernet block removes
preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit the
buffer NoDescriptor error probability, three descriptors are buffered. The value of the
RxProduceIndex is only updated after status information has been committed to memory,
which is checked by an internal tag protocol in the memory interface. The software device
driver will process the receive data, after which the device driver will update the
RxConsumeIndex.
For an RMII PHY the data between the Ethernet block and the PHY is communicated at
half the data-width and twice the clock frequency (50 MHz).
If a collision on the Ethernet occurs, it usually takes place during the collision window
spanning the first 64 bytes of a frame. If collision is detected, the Ethernet block will retry
the transmission. For this purpose, the first 64 bytes of a frame are buffered, so that this
data can be used during the retry. A transmission retry within the first 64 bytes in a frame
is fully transparent to the application and device driver software.
When a collision occurs outside of the 64 byte collision window, a LateCollision error is
triggered, and the transmission is aborted. After a LateCollision error, the remaining data
in the transmit frame will be discarded. The Ethernet block will set the Error and
LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will
be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the
IntStatus register will be propagated to the CPU (via the Vectored Interrupt Controller).
The device driver software should catch the interrupt and take appropriate actions.
The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure
the maximum number of retries before aborting the transmission.
For each received frame, the Ethernet block is able to detect the destination address and
source address and from them calculate the corresponding hash CRCs. To perform the
computation, the Ethernet block features two internal blocks: one is a controller
synchronized with the beginning and the end of each frame, the second block is the CRC
calculator.
When a new frame is detected, internal signaling notifies the controller.The controller
starts counting the incoming bytes of the frame, which correspond to the destination
address bytes. When the sixth (and last) byte is counted, the controller notifies the
calculator to store the corresponding 32 bit CRC into a first inner register. Then the
controller repeats counting the next incoming bytes, in order to get synchronized with the
source address. When the last byte of the source address is encountered, the controller
again notifies the CRC calculator, which freezes until the next new frame. When the
calculator receives this second notification, it stores the present 32 bit CRC into a second
inner register. Then the CRCs remain frozen in their own registers until new notifications
arise.
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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