LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 670

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
Table 593: A/D Control Register (AD0CR - address 0xE003 4000) bit description
UM10237_4
User manual
Bit
19:17 CLKS
20
21
23:22 -
26:24 START
27
31:28 -
Symbol
PDN
EDGE
5.2 A/D Global Data Register (AD0GDR - 0xE003 4004)
Value Description
000
001
010
011
100
101
110
111
1
0
000
001
010
011
100
101
110
111
1
0
The A/D Global Data Register contains the result of the most recent A/D conversion. This
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
This field selects the number of clocks used for each conversion in Burst mode, and the
number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks
(10 bits) and 4 clocks (3 bits).
11 clocks / 10 bits
10 clocks / 9 bits
9 clocks / 8 bits
8 clocks / 7 bits
7 clocks / 6 bits
6 clocks / 5 bits
5 clocks / 4 bits
4 clocks / 3 bits
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The A/D converter is operational.
The A/D converter is in Power-down mode.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When the BURST bit is 0, these bits control whether and when an A/D conversion is
started:
No start (this value should be used when clearing PDN to 0).
Start conversion now.
Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0.
Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1.
Start conversion when the edge selected by bit 27 occurs on MAT0.1.
Start conversion when the edge selected by bit 27 occurs on MAT0.3.
Start conversion when the edge selected by bit 27 occurs on MAT1.0.
Start conversion when the edge selected by bit 27 occurs on MAT1.1.
This bit is significant only when the START field contains 010-111. In these cases:
Start conversion on a falling edge on the selected CAP/MAT signal.
Start conversion on a rising edge on the selected CAP/MAT signal.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
000
NA
0
NA
0
0
NA