LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 21

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
4. APB peripheral addresses
UM10237_4
User manual
The following table shows the APB address map. No APB peripheral uses all of the 16 kB
space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple
locations within each 16 kB range.
Table 17.
APB Peripheral
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 to 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 to 126
127
APB peripherals and base addresses
Base Address
0xE000 0000
0xE000 4000
0xE000 8000
0xE000 C000
0xE001 0000
0xE001 4000
0xE001 8000
0xE001 C000
0xE002 0000
0xE002 4000
0xE002 8000
0xE002 C000
0xE003 0000
0xE003 4000
0xE003 8000
0xE003 C000
0xE004 0000
0xE004 4000
0xE004 8000
0xE004 C000 to 0xE005 8000
0xE005 C000
0xE006 0000
0xE006 4000
0xE006 8000
0xE006 C000
0xE007 0000
0xE007 4000
0xE007 8000
0xE007 C000
0xE008 0000
0xE008 4000
0xE008 8000
0xE008 C000
0xE009 0000 to 0xE01F BFFF
0xE01F C000
Rev. 04 — 26 August 2009
Chapter 2: LPC24XX Memory mapping
Peripheral Name
Watchdog Timer
Timer 0
Timer 1
UART0
UART1
PWM0
PWM1
I
SPI
RTC
GPIO
Pin Connect Block
SSP1
ADC
CAN Acceptance Filter RAM
CAN Acceptance Filter Registers
CAN Common Registers
CAN Controller 1
CAN Controller 2
Not used
I
Not used
Not used
SSP0
DAC
Timer 2
Timer 3
UART2
UART3
I
Battery RAM
I
SD/MMC Card Interface
Not used
System Control Block
2
2
2
2
C0
C1
C2
S
UM10237
© NXP B.V. 2009. All rights reserved.
21 of 792