LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 764

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
Table 176.GPIO Interrupt Enable for Rising edge register
Table 177.GPIO Interrupt Enable for Falling edge register
Table 178.GPIO Status for Rising edge register (IO0IntStatR
Table 179.GPIO Status for Falling edge register (IO0IntStatF
Table 180.GPIO Status for Falling edge register (IO0IntClr -
Table 181.Ethernet acronyms, abbreviations, and
Table 182.Example PHY Devices . . . . . . . . . . . . . . . . . .215
Table 183.Ethernet MII pin descriptions . . . . . . . . . . . . .217
Table 184.Ethernet RMII pin descriptions . . . . . . . . . . . .218
Table 185.Ethernet MIIM pin descriptions . . . . . . . . . . . .218
Table 186.Summary of Ethernet registers . . . . . . . . . . . .219
Table 187.MAC Configuration register 1 (MAC1 - address
Table 188.MAC Configuration register 2 (MAC2 - address
Table 189. Pad operation . . . . . . . . . . . . . . . . . . . . . . . .222
Table 190.Back-to-back Inter-packet-gap register (IPGT -
Table 191. Non Back-to-back Inter-packet-gap register
Table 192.Collision Window / Retry register (CLRT - address
Table 193.Maximum Frame register (MAXF - address
Table 194.PHY Support register (SUPP - address
Table 195. Test register (TEST - address 0xFFE0 ) bit
Table 196.MII Mgmt Configuration register (MCFG - address
Table 197. Clock select encoding . . . . . . . . . . . . . . . . . .225
Table 198.MII Mgmt Command register (MCMD - address
Table 199.MII Mgmt Address register (MADR - address
Table 200.MII Mgmt Write Data register (MWTD - address
Table 201.MII Mgmt Read Data register (MRDD - address
Table 202.MII Mgmt Indicators register (MIND - address
Table 203.Station Address register (SA0 - address
UM10237_4
User manual
- address 0xE002 8080) bit description . . . . .207
(IO0IntEnR - address 0xE002 8090 and
IO2IntEnR - address 0xE002 80B0)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .207
(IO0IntEnF - address 0xE002 8094 and
IO2IntEnF - address 0xE002 80B4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .207
- address 0xE002 8084 and IO2IntStatR - address
0xE002 80A4) bit description . . . . . . . . . . . . .208
- address 0xE002 8088 and IO2IntStatF - address
0xE002 80A8) bit description . . . . . . . . . . . . .208
address 0xE002 808C and IO2IntClr - address
0xE002 80AC) bit description . . . . . . . . . . . . .208
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
0xFFE0 0000) bit description . . . . . . . . . . . . .221
0xFFE0 0004) bit description . . . . . . . . . . . . .221
address 0xFFE0 0008) bit description . . . . . .223
(IPGR - address 0xFFE0 000C) bit description . .
223
0xFFE0 0010) bit description . . . . . . . . . . . . .224
0xFFE0 0014) bit description . . . . . . . . . . . . .224
0xFFE0 0018) bit description . . . . . . . . . . . . .224
description . . . . . . . . . . . . . . . . . . . . . . . . . . .225
0xFFE0 0020) bit description . . . . . . . . . . . . .225
0xFFE0 0024) bit description . . . . . . . . . . . . .226
0xFFE0 0028) bit description . . . . . . . . . . . . .226
0xFFE0 002C) bit description . . . . . . . . . . . . .226
0xFFE0 0030) bit description . . . . . . . . . . . . .226
0xFFE0 0034) bit description . . . . . . . . . . . . .227
0xFFE0 0040) bit description . . . . . . . . . . . . .227
Rev. 04 — 26 August 2009
Table 204.Station Address register (SA1 - address
Table 205.Station Address register (SA2 - address
Table 206.Command register (Command - address
Table 207.Status register (Status - address 0xFFE0 0104) bit
Table 208.Receive Descriptor Base Address register
Table 209.receive Status Base Address register (RxStatus -
Table 210.Receive Number of Descriptors register
Table 211. Receive Produce Index register (RxProduceIndex
Table 212.Receive Consume Index register
Table 213.Transmit Descriptor Base Address register
Table 214.Transmit Status Base Address register (TxStatus -
Table 215.Transmit Number of Descriptors register
Table 216.Transmit Produce Index register (TxProduceIndex
Table 217.Transmit Consume Index register
Table 218. Transmit Status Vector 0 register (TSV0 - address
Table 219.Transmit Status Vector 1 register (TSV1 - address
Table 220.Receive Status Vector register (RSV - address
Table 221.Flow Control Counter register
Table 222.Flow Control Status register (FlowControlStatus -
Table 223.Receive Filter Control register (RxFilterCtrl -
Table 224.Receive Filter WoL Status register
Table 225.Receive Filter WoL Clear register
Table 226.Hash Filter Table LSBs register (HashFilterL -
Table 227.Hash Filter MSBs register (HashFilterH - address
Table 228.Interrupt Status register (IntStatus - address
Chapter 36: LPC24XX Supplementary information
0xFFE0 0044) bit description . . . . . . . . . . . . . 228
0xFFE0 0048) bit description . . . . . . . . . . . . . 228
0xFFE0 0100) bit description . . . . . . . . . . . . . 228
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
(RxDescriptor - address 0xFFE0 0108) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
address 0xFFE0 010C) bit description. . . . . . 230
(RxDescriptor - address 0xFFE0 0110) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
- address 0xFFE0 0114) bit description . . . . . 230
(RXConsumeIndex - address 0xFFE0 0118) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
(TxDescriptor - address 0xFFE0 011C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
address 0xFFE0 0120) bit description . . . . . . 232
(TxDescriptorNumber - address 0xFFE0 0124) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
- address 0xFFE0 0128) bit description . . . . . 232
(TxConsumeIndex - address 0xFFE0 012C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
0xFFE0 0158) bit description . . . . . . . . . . . . . 233
0xFFE0 015C) bit description . . . . . . . . . . . . 234
0xFFE0 0160) bit description . . . . . . . . . . . . . 235
(FlowControlCounter - address 0xFFE0 0170) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
address 0xFFE0 8174) bit description . . . . . . 236
address 0xFFE0 0200) bit description . . . . . . 236
(RxFilterWoLStatus - address 0xFFE0 0204) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
(RxFilterWoLClear - address 0xFFE0 0208) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
address 0xFFE0 0210) bit description . . . . . . 238
0xFFE0 0214) bit description . . . . . . . . . . . . . 238
UM10237
© NXP B.V. 2009. All rights reserved.
764 of 792