LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 611

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

1. Basic configuration
2. Features
3. Description
UM10237_4
User manual
The I
The I
The I
select signal. The basic I
one slave. The I
channel, each of which can operate as either a master or a slave.
The I
channel. These support the NXP Inter IC Audio format for 8, 16 and 32 bits audio data
both for stereo and mono modes. Configuration, data access and control is performed by
a APB register set. Data streams are buffered by FIFOs with a depth of 8 bytes.
The I
mode. Within the I
(WS) signal which determines the timing of data transmissions. Data words start on the
1. Power: In the PCONP register
2. Clock: In PCLK_SEL1 select PCLK_I2S, see
3. Pins: Select I
4. Interrupts are enabled in the VIC using the VICIntEnable register
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UM10237
Chapter 23: LPC24XX I
Rev. 04 — 26 August 2009
Remark: On reset, the I
PINMODE4 (see
The I2S output can operate in both master and slave mode, independent of the I2S
input.
Capable of handling 8, 16, and 32 bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range (in practice) from 16 - 96 kHz. (16, 22.05, 32, 44.1,
48, 96 kHz) for audio applications.
Word Select period in master mode is configurable (separately for I
output).
Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the General Purpose DMA block.
Controls include reset, stop and mute options separately for I
2
2
2
2
2
S bus specification defines a 3-wire serial bus, having 1 data, 1 clock, and one word
S performs serial data out via the transmit channel and serial data in via the receive
S interface is configured using the following registers:
S bus provides a standard communication interface for digital audio applications.
S receive and transmit stage can operate independently in either slave or master
2
S interface on the LPC2400 provides a separate transmit and receive
2
S pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to
2
S module the difference between these modes lies in the word select
Section
Rev. 04 — 26 August 2009
2
S connection has one master, which is always the master, and
2
S interface is disabled (PCI2S = 0).
9–5).
2
(Table
S interface
4–63), set bit PCI2S.
Table
4–57.
2
S input and I
(Section
© NXP B.V. 2009. All rights reserved.
2
S input and I2S
User manual
7–3.4).
2
S output.
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