LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 392

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
Table 360. USB Host register address definitions
UM10237_4
User manual
Name
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFmRemaining
HcFmNumber
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
Address
0xFFE0 C000
0xFFE0 C004
0xFFE0 C008
0xFFE0 C00C
0xFFE0 C010
0xFFE0 C014
0xFFE0 C018
0xFFE0 C01C
0xFFE0 C020
0xFFE0 C024
0xFFE0 C028
0xFFE0 C02C
0xFFE0 C030
0xFFE0 C034
0xFFE0 C038
0xFFE0 C03C
0xFFE0 C040
0xFFE0 C044
0xFFE0 C048
0xFFE0 C04C
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R
R
R/W
R/W
R/W
R/W
[1]
Rev. 04 — 26 August 2009
Function
BCD representation of the version of the HCI
specification that is implemented by the Host Controller.
Defines the operating modes of the HC.
This register is used to receive the commands from the
Host Controller Driver (HCD). It also indicates the status
of the HC.
Indicates the status on various events that cause
hardware interrupts by setting the appropriate bits.
Controls the bits in the HcInterruptStatus register and
indicates which events will generate a hardware
interrupt.
The bits in this register are used to disable
corresponding bits in the HCInterruptStatus register and
in turn disable that event leading to hardware interrupt.
Contains the physical address of the host controller
communication area.
Contains the physical address of the current isochronous
or interrupt endpoint descriptor.
Contains the physical address of the first endpoint
descriptor of the control list.
Contains the physical address of the current endpoint
descriptor of the control list
Contains the physical address of the first endpoint
descriptor of the bulk list.
Contains the physical address of the current endpoint
descriptor of the bulk list.
Contains the physical address of the last transfer
descriptor added to the ‘Done’ queue.
Defines the bit time interval in a frame and the full speed
maximum packet size which would not cause an
overrun.
A 14-bit counter showing the bit time remaining in the
current frame.
Contains a 16-bit counter and provides the timing
reference among events happening in the HC and the
HCD.
Contains a programmable 14-bit value which determines
the earliest time HC should start processing a periodic
list.
Contains 11-bit value which is used by the HC to
determine whether to commit to transfer a maximum of
8-byte LS packet before EOF.
First of the two registers which describes the
characteristics of the root hub.
Second of the two registers which describes the
characteristics of the Root Hub.
Chapter 14: LPC24XX USB Host controller
UM10237
© NXP B.V. 2009. All rights reserved.
Reset value
0x10
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x2EDF
0x0
0x0
0x0
0x628h
0xFF000902
0x60000h
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