LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 75

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
10. Register description
Table 67.
UM10237_4
User manual
Address
0xFFE0 8000
0xFFE0 8004
0xFFE0 8008
0xFFE0 8020
0xFFE0 8024
0xFFE0 8028
0xFFE0 8030
0xFFE0 8034
0xFFE0 8038
0xFFE0 803C EMCDynamic APR
0xFFE0 8040
0xFFE0 8044
0xFFE0 8048
0xFFE0 804C EMCDynamic RFC
0xFFE0 8050
0xFFE0 8054
0xFFE0 8058
0xFFE0 8080
0xFFE0 8100
0xFFE0 8104
0xFFE0 8120
Summary of EMC registers
Register Name
EMCControl
EMCStatus
EMCConfig
EMCDynamic Control
EMCDynamic Refresh
EMCDynamic ReadConfig Configures the dynamic memory read strategy.
EMCDynamicRP
EMCDynamic RAS
EMCDynamic SREX
EMCDynamic DAL
EMCDynamicWR
EMCDynamicRC
EMCDynamic XSR
EMCDynamic RRD
EMCDynamic MRD
EMCStatic ExtendedWait
EMCDynamic Config0
EMCDynamic RasCas0
EMCDynamic Config1
Table 66.
This chapter describes the EMC registers and provides details required when
programming the microcontroller. The EMC registers are shown in
Name
CLKOUT[1:0]
CKEOUT[3:0]
DQMOUT[3:0]
Pad interface and control signal descriptions
Description
Controls operation of the memory controller.
Provides EMC status information.
Configures operation of the memory controller
Controls dynamic memory operation.
Configures dynamic memory refresh operation.
Selects the precharge command period.
Selects the active to precharge command period.
Selects the self-refresh exit time.
Selects the last-data-out to active command time.
Selects the data-in to active command time.
Selects the write recovery time.
Selects the active to active command period.
Selects the auto-refresh period.
Selects the exit self-refresh to active command time.
Selects the active bank A to active bank B latency.
Selects the load mode register to active command time. -
Selects time for long static memory read and write
transfers.
Selects the configuration information for dynamic
memory chip select 0.
Selects the RAS and CAS latencies for dynamic memory
chip select 0.
Selects the configuration information for dynamic
memory chip select 1.
Output 0xF
Type
Output Follows CCLK Follows CCLK SDRAM clocks. Used for SDRAM
Output 0xF
Rev. 04 — 26 August 2009
Value on POR
reset
Chapter 5: LPC24XX External Memory Controller (EMC)
Value during
self-refresh
0x0
0xF
Description
devices.
SDRAM clock enables. Used for
SDRAM devices. One is allocated for
each Chip Select.
Data mask output to SDRAMs. Used
for SDRAM devices and static
memories.
Table
Warm
Reset
Value
[1]
0x1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UM10237
© NXP B.V. 2009. All rights reserved.
5–67.
POR
Reset
Value
[1]
0x3
0x5
0x0
0x006 R/W
0x0
0x0
0x0F
0xF
0xF
0xF
0xF
0xF
0x1F
0x1F
0x1F
0xF
0xF
0x0
0x0
0x303 R/W
0x0
75 of 792
Type
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W