LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 779

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.1.16
7.1.17
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
UM10237_4
User manual
Back-to-Back Inter-Packet-Gap Register (IPGT -
0xFFE0 0008) . . . . . . . . . . . . . . . . . . . . . . . . 223
Non Back-to-Back Inter-Packet-Gap Register
(IPGR - 0xFFE0 000C) . . . . . . . . . . . . . . . . . 223
Collision Window / Retry Register (CLRT -
0xFFE0 0010) . . . . . . . . . . . . . . . . . . . . . . . . 223
Maximum Frame Register (MAXF -
0xFFE0 0014) . . . . . . . . . . . . . . . . . . . . . . . . 224
PHY Support Register (SUPP -
0xFFE0 0018) . . . . . . . . . . . . . . . . . . . . . . . . 224
Test Register (TEST - 0xFFE0 001C). . . . . . 224
MII Mgmt Configuration Register (MCFG -
0xFFE0 0020) . . . . . . . . . . . . . . . . . . . . . . . . 225
MII Mgmt Command Register (MCMD -
0xFFE0 0024) . . . . . . . . . . . . . . . . . . . . . . . . 225
MII Mgmt Address Register (MADR -
0xFFE0 0028) . . . . . . . . . . . . . . . . . . . . . . . . 226
MII Mgmt Write Data Register (MWTD -
0xFFE0 002C) . . . . . . . . . . . . . . . . . . . . . . . 226
MII Mgmt Read Data Register (MRDD -
0xFFE0 0030) . . . . . . . . . . . . . . . . . . . . . . . . 226
MII Mgmt Indicators Register (MIND -
0xFFE0 0034) . . . . . . . . . . . . . . . . . . . . . . . . 226
Station Address 0 Register (SA0 -
0xFFE0 0040) . . . . . . . . . . . . . . . . . . . . . . . . 227
Station Address 1 Register (SA1 -
0xFFE0 0044) . . . . . . . . . . . . . . . . . . . . . . . . 227
Station Address 2 Register (SA2 -
0xFFE0 0048) . . . . . . . . . . . . . . . . . . . . . . . . 228
Command Register (Command -
0xFFE0 0100) . . . . . . . . . . . . . . . . . . . . . . . . 228
Status Register (Status - 0xFFE0 0104) . . . . 229
Receive Descriptor Base Address Register
(RxDescriptor - 0xFFE0 0108) . . . . . . . . . . . 229
Receive Status Base Address Register (RxStatus
- 0xFFE0 010C) . . . . . . . . . . . . . . . . . . . . . . 230
Receive Number of Descriptors Register
(RxDescriptor - 0xFFE0 0110) . . . . . . . . . . . 230
Receive Produce Index Register
(RxProduceIndex - 0xFFE0 0114) . . . . . . . . 230
Receive Consume Index Register
(RxConsumeIndex - 0xFFE0 0118) . . . . . . . 231
Transmit Descriptor Base Address Register
(TxDescriptor - 0xFFE0 011C) . . . . . . . . . . . 231
Transmit Status Base Address Register (TxStatus
- 0xFFE0 0120). . . . . . . . . . . . . . . . . . . . . . . 231
Transmit Number of Descriptors Register
(TxDescriptorNumber - 0xFFE0 0124) . . . . . 232
Transmit Produce Index Register
(TxProduceIndex - 0xFFE0 0128) . . . . . . . . 232
Transmit Consume Index Register
(TxConsumeIndex - 0xFFE0 012C) . . . . . . . 233
Transmit Status Vector 0 Register (TSV0 -
0xFFE0 0158) . . . . . . . . . . . . . . . . . . . . . . . . 233
Transmit Status Vector 1 Register (TSV1 -
0xFFE0 015C) . . . . . . . . . . . . . . . . . . . . . . . 234
Control register definitions . . . . . . . . . . . . . . 228
Rev. 04 — 26 August 2009
7.2.15
7.2.16
7.2.17
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
8
8.1
8.2
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
9.16
9.17
9.18
9.19
9.20
9.21
9.22
9.23
9.23.1
9.23.2
9.23.3
Chapter 36: LPC24XX Supplementary information
Descriptor and status formats . . . . . . . . . . . 241
Ethernet block functional description. . . . . 247
Receive Status Vector Register (RSV -
0xFFE0 0160) . . . . . . . . . . . . . . . . . . . . . . . 234
Flow Control Counter Register
(FlowControlCounter - 0xFFE0 0170) . . . . . 235
Flow Control Status Register (FlowControlStatus -
0xFFE0 0174) . . . . . . . . . . . . . . . . . . . . . . . 236
Receive filter register definitions . . . . . . . . . 236
Receive Filter Control Register (RxFilterCtrl -
0xFFE0 0200) . . . . . . . . . . . . . . . . . . . . . . . 236
Receive Filter WoL Status Register
(RxFilterWoLStatus - 0xFFE0 0204) . . . . . . 237
Receive Filter WoL Clear Register
(RxFilterWoLClear - 0xFFE0 0208) . . . . . . . 237
Hash Filter Table LSBs Register (HashFilterL -
0xFFE0 0210) . . . . . . . . . . . . . . . . . . . . . . . 238
Hash Filter Table MSBs Register (HashFilterH -
0xFFE0 0214) . . . . . . . . . . . . . . . . . . . . . . . 238
Module control register definitions . . . . . . . . 238
Interrupt Status Register (IntStatus -
0xFFE0 0FE0) . . . . . . . . . . . . . . . . . . . . . . . 238
Interrupt Enable Register (IntEnable -
0xFFE0 0FE4) . . . . . . . . . . . . . . . . . . . . . . . 239
Interrupt Clear Register (IntClear -
0xFFE0 0FE8) . . . . . . . . . . . . . . . . . . . . . . . 240
Interrupt Set Register (IntSet -
0xFFE0 0FEC) . . . . . . . . . . . . . . . . . . . . . . . 240
Power-Down Register (PowerDown -
0xFFE0 0FF4) . . . . . . . . . . . . . . . . . . . . . . . 241
Receive descriptors and statuses . . . . . . . . 241
Transmit descriptors and statuses . . . . . . . . 245
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
AHB interface. . . . . . . . . . . . . . . . . . . . . . . . 248
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Direct Memory Access (DMA) . . . . . . . . . . . 248
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 251
Transmit process . . . . . . . . . . . . . . . . . . . . . 252
Receive process . . . . . . . . . . . . . . . . . . . . . 258
Transmission retry . . . . . . . . . . . . . . . . . . . . 264
Status hash CRC calculations . . . . . . . . . . . 264
Duplex modes . . . . . . . . . . . . . . . . . . . . . . . 265
IEE 802.3/Clause 31 flow control. . . . . . . . . 265
Half-Duplex mode backpressure . . . . . . . . . 267
Receive filtering . . . . . . . . . . . . . . . . . . . . . . 268
Power management. . . . . . . . . . . . . . . . . . . 270
Wake-up on LAN . . . . . . . . . . . . . . . . . . . . . 271
Enabling and disabling receive and transmit 272
Transmission padding and CRC . . . . . . . . . 274
Huge frames and frame length checking . . . 275
Statistics counters . . . . . . . . . . . . . . . . . . . . 275
MAC status vectors . . . . . . . . . . . . . . . . . . . 275
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Ethernet errors . . . . . . . . . . . . . . . . . . . . . . . 277
AHB bandwidth . . . . . . . . . . . . . . . . . . . . . . 277
DMA access. . . . . . . . . . . . . . . . . . . . . . . . . 277
Types of CPU access. . . . . . . . . . . . . . . . . . 279
Overall bandwidth . . . . . . . . . . . . . . . . . . . . 279
UM10237
© NXP B.V. 2009. All rights reserved.
779 of 792