LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 638

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
Table 557. PWM0 and PWM1 register map
UM10237_4
User manual
Generic
Name
IR
TCR
TC
PR
PC
MCR
MR0
MR1
MR2
MR3
CCR
CR0
CR1
Description
Interrupt Register. The IR can be written to clear
interrupts. The IR can be read to identify which of eight
possible interrupt sources are pending.
Timer Control Register. The TCR is used to control the
Timer Counter functions. The Timer Counter can be
disabled or reset through the TCR.
Timer Counter. The 32 bit TC is incremented every PR+1
cycles of PCLK. The TC is controlled through the TCR.
Prescale Register. The TC is incremented every PR+1
cycles of PCLK.
Prescale Counter. The 32 bit PC is a counter which is
incremented to the value stored in PR. When the value in
PR is reached, the TC is incremented. The PC is
observable and controllable through the bus interface.
Match Control Register. The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match
occurs.
Match Register 0. MR0 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC sets any PWM output that
is in single-edge mode, and sets PWM1 if it’s in
double-edge mode.
Match Register 1. MR1 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM1 in either
edge mode, and sets PWM2 if it’s in double-edge mode.
Match Register 2. MR2 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM2 in either
edge mode, and sets PWM3 if it’s in double-edge mode.
Match Register 3. MR3 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM3 in either
edge mode, and sets PWM4 if it’s in double-edge mode.
Capture Control Register. The CCR controls which edges
of the capture inputs are used to load the Capture
Registers and whether or not an interrupt is generated
when a capture takes place.
Capture Register 0. PWMn CR0 is loaded with the value
of the TC when there is an event on the CAPn.0 input.
Capture Register 1. See CR0 description.
Rev. 04 — 26 August 2009
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Access Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
0
Value
0
0
0
0
0
0
0
0
0
0
0
0
[1]
PWM0 Address
& Name
0xE001 4000
PWM0IR
0xE001 4004
PWM0TCR
0xE001 4008
PWM0TC
0xE001 400C
PWM0PR
0xE000 4010
PWM0PC
0xE001 4014
PWM0MCR
0xE001 4018
PWM0MR0
0xE001 401C
PWM0MR1
0xE001 4020
PWM0MR2
0xE001 4024
PWM0MR3
0xE001 4028
PWM0CCR
0xE001 402C
PWM0CR0
0xE001 4030
PWM0CR1
UM10237
© NXP B.V. 2009. All rights reserved.
PWM1 Address
& Name
0xE001 8000
PWM1IR
0xE001 8004
PWM1TCR
0xE001 8008
PWM1TC
0xE001 800C
PWM1PR
0xE001 8010
PWM1PC
0xE001 8014
PWM0MCR
0xE001 8018
PWM1MR0
0xE001 801C
PWM1MR1
0xE001 8020
PWM1MR2
0xE001 8024
PWM1MR3
0xE001 8028
PWM1CCR
-
0xE001 8030
PWM1CR1
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