LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 297

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
6.5.6 Cursor image format
The LCD frame buffer supports three packing formats, but the hardware cursor image
requirement has been simplified to support only LBBP. This is little-endian byte,
big-endian pixel for Windows CE mode.
The Image RAM start address is offset by 0x800 from the LCD base address, as shown in
the register description in this chapter.
The displayed cursor coordinate system is expressed in terms of (X,Y). 64 x 64 is an
extension of the 32 x 32 format shown in
32 by 32 pixel format
Four cursors are held in memory, each with the same pixel format.
base addresses for the four cursors.
Table 254. Addresses for 32 x 32 cursors
Address
0xFFE1 0800
0xFFE1 0900
0xFFE1 0A00
0xFFE1 0B00
Fig 39. Cursor image format
LEFT
(0, 29)
(0, 30)
(0, 31)
(0, 0)
(0, 1)
(0, 2)
Rev. 04 — 26 August 2009
(1, 29)
(1, 30)
(1, 31)
(1, 0)
(1, 1)
(1, 2)
Description
Cursor 0 start address.
Cursor 1 start address.
Cursor 2 start address.
Cursor 3 start address.
(2, 29)
(2, 30)
(2, 31)
(2, 0)
(2, 1)
(2, 2)
BOTTOM
Figure
TOP
12–39.
(29, 29)
(29, 30)
(29, 31)
(29, 0)
(29, 1)
(29, 2)
Chapter 12: LPC24XX LCD controller
(30, 29)
(30, 30)
(30, 31)
(30, 0)
(30, 1)
(30, 2)
(31, 29)
(31, 30)
(31, 31)
(31, 0)
(31, 1)
(31, 2)
Table 12–254
UM10237
© NXP B.V. 2009. All rights reserved.
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