LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 495

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
10. Centralized CAN registers
UM10237_4
User manual
10.1 Central Transmit Status Register (CANTxSR - 0xE004 0000)
9.3 Interrupts
9.4 Transmit priority
The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the
CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b)
software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up
in response to bus activity, is not able to receive an initial message, until after it detects
Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is
active when software sets SM, the wake-up is immediate.
Each CAN Controller produces interrupt requests for Receive, Transmit, and “other
status”. The Transmit interrupt is the OR of the Transmit interrupts from the three Tx
Buffers. The Receive, Transmit, and “other status” interrupts from all of the CAN
controllers and the Acceptance Filter LUTerr condition are ORed into one VIC channel
(see
If the TPM bit in the CANxMOD register is 0, multiple enabled Tx Buffers contend for the
right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1,
they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In both
cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have
the same smallest value, the lowest-numbered buffer sends first.
The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it
sends each message.
For easy and fast access, all CAN Controller Status bits from each CAN Controller Status
register are bundled together. Each defined byte of the following registers contains one
particular status bit from each of the CAN controllers, in its LS bits.
All Status registers are “read-only” and allow byte, half word and word access.
Table 438. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description
Bit
0
1
7:2
8
9
15:10 -
Table
Symbol
TS1
TS2
-
TBS1
TBS2
7–116).
Description
When 1, the CAN controller 1 is sending a message (same as TS in the
CAN1GSR).
When 1, the CAN controller 2 is sending a message (same as TS in the
CAN2GSR)
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU
(same as TBS in CAN1GSR).
When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU
(same as TBS in CAN2GSR).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
0
0
NA
1
1
NA