LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 761

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
3. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. LPC2470 ordering options . . . . . . . . . . . . . . . . .8
Table 11. LPC2478 ordering information . . . . . . . . . . . . . .8
Table 12. LPC2478 ordering options . . . . . . . . . . . . . . . . .8
Table 13. LPC2400 memory options and addressing. . . .16
Table 14. LPC2458 memory usage and details . . . . . . . .16
Table 15. LPC2420/60/70 memory usage and details . . .17
Table 16. LPC2468/78 memory usage and details. . . . . .17
Table 17. APB peripherals and base addresses . . . . . . .21
Table 18. ARM exception vector locations . . . . . . . . . . . .22
Table 19. LPC2400 Memory mapping modes . . . . . . . . .23
Table 20. Memory mapping control registers . . . . . . . . . .24
Table 21. Memory Mapping control register (MEMMAP -
Table 22. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 23. Summary of system control registers . . . . . . . .27
Table 24. External Interrupt registers . . . . . . . . . . . . . . . .28
Table 25. External Interrupt Flag register (EXTINT - address
Table 26. External Interrupt Mode register (EXTMODE -
Table 27. External Interrupt Polarity register (EXTPOLAR -
Table 28. Reset Source Identification register (RSID -
Table 29. AHB configuration register map . . . . . . . . . . . .34
Table 30. AHB Arbiter Configuration register 1 (AHBCFG1 -
Table 31. Priority sequence (bit 0 = 0): LCD, CPU, GPDMA,
Table 32. Priority sequence (bit 0 = 0): USB, AHB1, CPU,
Table 33. Priority sequence (bit 0 = 0): GPDMA, AHB1,
Table 34. Priority sequence (bit 0 = 0): USB, LCD, AHB1,
Table 35. AHB Arbiter Configuration register 2 (AHBCFG2 -
Table 36. Priority sequence (bit 0 = 0): Ethernet, CPU . .38
Table 37. Priority sequence (bit 0 = 0): Ethernet, CPU . .38
Table 38. System Controls and Status register (SCS -
Table 39. Recommended values for C
Table 40. Recommended values for C
UM10237_4
User manual
LPC24XX overview. . . . . . . . . . . . . . . . . . . . . . .3
Differences between LPC2400 parts . . . . . . . . .4
LPC2458 ordering information . . . . . . . . . . . . . .6
LPC2458 ordering options . . . . . . . . . . . . . . . . .6
LPC2420/60 ordering information . . . . . . . . . . .6
LPC2420/60 ordering options . . . . . . . . . . . . . .7
LPC2468 ordering information . . . . . . . . . . . . . .7
LPC2468 ordering options . . . . . . . . . . . . . . . . .7
LPC2470 ordering information . . . . . . . . . . . . . .7
address 0xE01F C040) bit description . . . . . . .24
0xE01F C140) bit description . . . . . . . . . . . . . .29
address 0xE01F C148) bit description . . . . . . .30
address 0xE01F C14C) bit description . . . . . . .31
address 0xE01F C180) bit description . . . . . . .34
address 0xE01F C188) bit description . . . . . . .35
AHB1, USB. . . . . . . . . . . . . . . . . . . . . . . . . . . .36
GPDMA, LCD . . . . . . . . . . . . . . . . . . . . . . . . . .36
CPU, LCD, USB . . . . . . . . . . . . . . . . . . . . . . . .36
CPU, GPDMA . . . . . . . . . . . . . . . . . . . . . . . . . .36
address 0xE01F C18C) bit description . . . . . . .37
address 0xE01F C1A0) bit description . . . . . . .38
mode (crystal and external components
parameters) low frequency mode (OSCRANGE =
0, see
mode (crystal and external components
Table
3–38) . . . . . . . . . . . . . . . . . . . . . .44
X1/X2
X1/X2
in oscillation
in oscillation
Rev. 04 — 26 August 2009
Table 41. Summary of system control registers. . . . . . . . 45
Table 42. Clock Source Select register (CLKSRCSEL -
Table 43. PLL registers . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 44. PLL Control register (PLLCON - address
Table 45. PLL Configuration register (PLLCFG - address
Table 46. Multiplier values for a 32 kHz oscillator . . . . . . 50
Table 47. PLL Status register (PLLSTAT - address
Table 48. PLL control bit combinations . . . . . . . . . . . . . . 52
Table 49. PLL Feed register (PLLFEED - address
Table 50. PLL frequency parameter . . . . . . . . . . . . . . . . 53
Table 51. Additional Multiplier Values for use with a Low
Table 52. Potential values for PLL example . . . . . . . . . . 56
Table 53. CPU Clock Configuration register (CCLKCFG -
Table 54. USB Clock Configuration register (USBCLKCFG -
Table 55. IRC Trim register (IRCTRIM - address
Table 56. Peripheral Clock Selection register 0 (PCLKSEL0
Table 57. Peripheral Clock Selection register 1 (PCLKSEL1
Table 58. Peripheral Clock Selection register bit values . 60
Table 59. Power Control registers . . . . . . . . . . . . . . . . . . 62
Table 60. Power Mode Control register (PCON - address
Table 61. Encoding of reduced power modes . . . . . . . . . 63
Table 62. Interrupt Wakeup register (INTWAKE - address
Table 63. Power Control for Peripherals register (PCONP -
Table 64. EMC configuration . . . . . . . . . . . . . . . . . . . . . . 68
Table 65. Memory bank selection
Table 66. Pad interface and control signal descriptions . 74
Table 67. Summary of EMC registers . . . . . . . . . . . . . . . 75
Table 68. EMC Control register (EMCControl - address
Table 69. EMC Status register (EMCStatus - address
Table 70. EMC Configuration register (EMCConfig -
Table 71. Dynamic Control register (EMCDynamicControl -
Table 72. Dynamic Memory Refresh Timer register
Table 73. Dynamic Memory Read Configuration register
Chapter 36: LPC24XX Supplementary information
parameters) high frequency mode (OSCRANGE =
1, see
address 0xE01F C10C) bit description . . . . . . 46
0xE01F C080) bit description. . . . . . . . . . . . . . 49
0xE01F C084) bit description. . . . . . . . . . . . . . 49
0xE01F C088) bit description. . . . . . . . . . . . . . 52
0xE01F C08C) bit description . . . . . . . . . . . . . 53
Frequency Clock Input . . . . . . . . . . . . . . . . . . . 54
address 0xE01F C104) bit description. . . . . . . 57
address 0xE01F C108) bit description. . . . . . . 58
0xE01F C1A4) bit description . . . . . . . . . . . . . 58
- address 0xE01F C1A8) bit description . . . . . 58
- address 0xE01F C1AC) bit description . . . . . 59
0xE01F C0C0) bit description . . . . . . . . . . . . . 62
0xE01F C144) bit description. . . . . . . . . . . . . . 64
address 0xE01F C0C4) bit description . . . . . . 65
0xFFE0 8000) bit description . . . . . . . . . . . . . . 77
0xFFE0 8008) bit description . . . . . . . . . . . . . . 78
address 0xFFE0 8008) bit description . . . . . . . 79
address 0xFFE0 8020) bit description . . . . . . . 79
(EMCDynamicRefresh - address 0xFFE0 8024)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 81
(EMCDynamicReadConfig - address
Table
3–38) . . . . . . . . . . . . . . . . . . . . . . 44
[1]
. . . . . . . . . . . . . . . . . 73
UM10237
© NXP B.V. 2009. All rights reserved.
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