LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 79

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
10.3 EMC Configuration register (EMCConfig - 0xFFE0 8008)
10.4 Dynamic Memory Control register (EMCDynamicControl -
The EMCConfig register configures the operation of the memory controller. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This register is accessed with one
wait state.
Table 70.
0xFFE0 8020)
The EMCDynamicControl register controls dynamic memory operation. The control bits
can be altered during normal operation.
EMCDynamicControl register.
Table 71.
Bit
0
7:1
8
31:9 -
Bit
0
1
Symbol
-
Symbol
Dynamic
memory clock
enable (CE)
Dynamic
memory clock
control (CS)
Table 5–70
EMC Configuration register (EMCConfig - address 0xFFE0 8008) bit description
Dynamic Control register (EMCDynamicControl - address 0xFFE0 8020) bit
description
Rev. 04 — 26 August 2009
shows the bit assignments for the EMCConfig register.
Value Description
0
1
-
0
1
-
Value Description
0
1
0
1
Endian mode:
Little-endian mode (POR reset value).
Big-endian mode.
On power-on reset, the value of the endian bit is 0. All
data must be flushed in the EMC before switching
between little-endian and big-endian modes.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
CCLK : CLKOUT[1:0] ratio:
1:1 (POR reset value)
1:2 (this option is not available on the LPC2400)
This bit must contain 0 for proper operation of the EMC.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 5: LPC24XX External Memory Controller (EMC)
Clock enable of idle devices are deasserted to save
power (POR reset value).
All clock enables are driven HIGH continuously.
CLKOUT stops when all SDRAMs are idle and during
self-refresh mode.
CLKOUT runs continuously (POR reset value).
When clock control is LOW the output clock CLKOUT is
stopped when there are no SDRAM transactions. The
clock is also stopped during self-refresh mode.
Table 5–71
shows the bit assignments for the
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
0
NA
0
NA
Reset
Value
0
1