LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 374

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
14. DMA operation
UM10237_4
User manual
13.3 Data transfer for IN endpoints
14.1 Transfer terminology
endpoints, the next packet will be received irrespective of whether the buffer has been
cleared. Any data not read from the buffer before the end of the frame is lost. See
Section 13–15 “Double buffered endpoint operation”
If the software clears RD_EN before the entire packet is read, reading is terminated, and
the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the
data will be read from the beginning.
When writing data to an endpoint buffer, WR_EN
(USBCtrl - 0xFFE0
send in the packet to the USBTxPLen register
continuously in the USBTxData register.
When the the number of bytes programmed in USBTxPLen have been written to
USBTxData, the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt
register. Software issues a Validate Buffer
0xFA, Data:
isochronous endpoints, the data in the buffer will be sent only if the buffer is validated
before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the
next frame. If the software clears WR_EN before the entire packet is written, writing will
start again from the beginning the next time WR_EN is set for this endpoint.
Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.
Interleaved read and write operation is possible.
In DMA mode, the DMA transfers data between RAM and the endpoint buffer.
The following sections discuss DMA mode operation. Background information is given in
sections
“Triggering the DMA
Section 13–14.4 “The DMA
Section 13–14.5 “Non-isochronous endpoint
endpoint
operation”.
Within this section three types of transfers are mentioned:
1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers
2. DMA transfers – the transfer of data between an endpoint buffer and system memory
3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of
to these simply as transfers. Within this section they are referred to as USB transfers
to distinguish them from DMA transfers. A USB transfer is composed of transactions.
Each transaction is composed of packets.
(RAM).
data between an endpoint buffer and system memory (RAM). A DMA transfer is
composed of one or more packet transfers.
Section 13–14.2 “USB device communication area”
operation”, and
none)”) command. The endpoint is now ready to send the packet. For IN
C228)”) is set and software writes to the number of bytes it is going to
engine”. The fields of the DMA Descriptor are described in section
Rev. 04 — 26 August 2009
Section 13–14.7 “Auto Length Transfer Extraction (ATLE) mode
descriptor”. The last three sections describe DMA operation:
Chapter 13: LPC24XX USB device controller
(Section 13–11.14 “Validate Buffer (Command:
operation”,
(Section
(Section 13–9.6.5 “USB Control register
for more details.
13–9.6.4). It can then write data
Section 13–14.6 “Isochronous
and
Section 13–14.3
UM10237
© NXP B.V. 2009. All rights reserved.
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