LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 52

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
3.2.7 PLL Interrupt: PLOCK
3.2.8 PLL Modes
Table 47.
The PLOCK bit in the PLLSTAT register reflects the lock status of the PLL. When the PLL
is enabled, or parameters are changed, the PLL requires some time to establish lock
under the new conditions. PLOCK can be monitored to determine when the PLL may be
connected for use. The value of PLOCK may not be stable when the PLL reference
frequency (F
divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these
cases, the PLL may be assumed to be stable after a start-up time has passed. This time is
500 μs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less
than 400 kHz
PLOCK is connected to the interrupt controller. This allows for software to turn on the PLL
and continue with other functions without having to wait for the PLL to achieve lock. When
the interrupt occurs, the PLL may be connected, and the interrupt disabled.
The combinations of PLLE and PLLC are shown in
Table 48.
Bit
14:0
15
23:16 NSEL
24
25
26
31:27 -
PLLC
0
0
1
1
Symbol
MSEL
-
PLLE
PLLC
PLOCK
PLLE
0
1
0
1
PLL Status register (PLLSTAT - address 0xE01F C088) bit description
PLL control bit combinations
REF
, the frequency of REFCLK, which is equal to the PLL input frequency
PLL Function
PLL is turned off and disconnected. The PLL outputs the unmodified clock
input.
The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.
Same as 00 combination. This prevents the possibility of the PLL being
connected without also being enabled.
The PLL is active and has been connected as the system clock source.
Description
Read-back for the PLL Multiplier value. This is the value currently
used by the PLL, and is one less than the actual multiplier.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Read-back for the PLL Pre-Divider value. This is the value currently
used by the PLL, and is one less than the actual divider.
Read-back for the PLL Enable bit. When one, the PLL is currently
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power-down mode is activated.
Read-back for the PLL Connect bit. When PLLC and PLLE are both
one, the PLL is connected as the clock source for the LPC2400.
When either PLLC or PLLE is zero, the PLL is bypassed. This bit is
automatically cleared when Power-down mode is activated.
Reflects the PLL Lock status. When zero, the PLL is not locked.
When one, the PLL is locked onto the requested frequency. See
text for details.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 4: LPC24XX Clocking and power control
Table
4–48.
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
value
0
NA
0
0
0
0
NA
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