LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 644

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
6.6 PWM Control Registers (PWM0PCR - 0xE001 404C and PWM1PCR
Table 562: PWM Capture Control Register (PWM0CCR - address 0xE001 4028 and PWM1CCR
[1]
0xE001 804C)
The PWM Control registers are used to enable and select the type of each PWM channel.
The function of each of the bits are shown in
Table 563: PWM Control Registers (PWMPCR - address 0xE001 404C and PWM1PCR
Bit
3
4
5
31:6 -
Bit
1:0
2
3
4
5
6
8:7
9
10
11
12
13
14
31:15 Unused
Reserved for PWM0.
Symbol
Capture on
PCAPn.1
rising edge
Capture on
PCAPn.1
falling edge
Interrupt on
PCAPn.1
event
Symbol
Unused
PWMSEL2
PWMSEL3 1
PWMSEL4 1
PWMSEL5 1
PWMSEL6 1
-
PWMENA1
PWMENA2
PWMENA3
PWMENA4
PWMENA5
PWMENA6
address 0xE001 8028) bit description
[1]
address 0xE001 804C) bit description
[1]
[1]
Value Description
1
0
0
1
Value Description
0
1
0
1
0
1
Rev. 04 — 26 August 2009
Unused, always zero.
PWM2 output single/double edge mode control.
Double edge controlled mode is selected.
Single edge controlled mode is selected.
PWM3 output edge control. See PWMSEL2 for details.
PWM4 output edge control. See PWMSEL2 for details.
PWM5 output edge control. See PWMSEL2 for details.
PWM6 output edge control. See PWMSEL2 for details.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
The PWM1 output enable control.
The PWM output is disabled.
The PWM output is enabled.
The PWM2 output enable control. See PWMENA1 for details. 0
The PWM3 output enable control. See PWMENA1 for details. 0
The PWM4 output enable control. See PWMENA1 for details. 0
The PWM5 output enable control. See PWMENA1 for details. 0
The PWM6 output enable control. See PWMENA1 for details. 0
Unused, always zero.
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
This feature is disabled.
A synchronously sampled rising edge on the PCAPn.1 input
will cause CR1 to be loaded with the contents of the TC.
This feature is disabled.
A synchronously sampled falling edge on PCAPn.1 will cause
CR1 to be loaded with the contents of TC.
This feature is disabled.
A CR1 load due to a PCAPn.1 event will generate an
interrupt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Table
25–563.
UM10237
© NXP B.V. 2009. All rights reserved.
644 of 792
Reset
Value
0
0
0
NA
Reset
Value
NA
0
0
0
0
0
NA
0
NA