LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 305

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
7.2.1 Horizontal timing restrictions
Table 261. Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000)
DMA requests new data at the start of a horizontal display line. Some time must be
allowed for the DMA transfer and for data to propagate down the FIFO path in the LCD
interface. The data path latency forces some restrictions on the usable minimum values
for horizontal porch width in STN mode. The minimum values are HSW = 2 and HBP = 2.
Single panel mode:
Dual panel mode:
Bits
31:24
23:16
15:8
7:2
1:0
•
•
•
•
•
•
•
HSW = 3 pixel clock cycles
HBP = 5 pixel clock cycles
HFP = 5 pixel clock cycles
Panel Clock Divisor (PCD) = 1 (LCDCLK / 3)
HSW = 3 pixel clock cycles
HBP = 5 pixel clock cycles
HFP = 5 pixel clock cycles
Function
HBP
HFP
HSW
PPL
reserved
Rev. 04 — 26 August 2009
Description
Horizontal back porch.
The 8-bit HBP field is used to specify the number of pixel clock
periods inserted at the beginning of each line or row of pixels.
After the line clock for the previous line has been deasserted, the
value in HBP counts the number of pixel clocks to wait before
starting the next display line. HBP can generate a delay of 1-256
pixel clock cycles. Program with desired value minus 1.
Horizontal front porch.
The 8-bit HFP field sets the number of pixel clock intervals at the
end of each line or row of pixels, before the LCD line clock is
pulsed. When a complete line of pixels is transmitted to the LCD
driver, the value in HFP counts the number of pixel clocks to wait
before asserting the line clock. HFP can generate a period of
1-256 pixel clock cycles. Program with desired value minus 1.
Horizontal synchronization pulse width.
The 8-bit HSW field specifies the pulse width of the line clock in
passive mode, or the horizontal synchronization pulse in active
mode. Program with desired value minus 1.
Pixels-per-line.
The PPL bit field specifies the number of pixels in each line or
row of the screen. PPL is a 6-bit value that represents between
16 and 1024 pixels per line. PPL counts the number of pixel
clocks that occur before the HFP is applied.
Program the value required divided by 16, minus 1. Actual
pixels-per-line = 16 * (PPL + 1). For example, to obtain 320
pixels per line, program PPL as (320/16) -1 = 19.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 12: LPC24XX LCD controller
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0x0
0x0
0x0
0x0
-