MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet
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MCF5270CAB100 Summary of contents
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MCF5271 Reference Manual Devices Supported: MCF5270 MCF5271 Document Number: MCF5271RM Rev. 2 07/2006 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...
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Enhanced Multiply-Accumulate Unit (EMAC) Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) General Purpose I/O Module Interrupt Controller Modules Edge Port Module (EPORT) External Interface Module (EIM) Synchronous DRAM Controller Fast Ethernet Controller (FEC) Watchdog Timer Module ...
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Overview 2 Signal Descriptions 3 ColdFire Core 4 Enhanced Multiply-Accumulate Unit (EMAC) 5 Cache 6 Static RAM (SRAM) 7 Clock Module 8 Power Management 9 Chip Configuration Module (CCM) 10 Reset Controller Module System Control Module (SCM ...
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... GPIO ......................................................................................................................... 1-12 1.4 Documentation.............................................................................................................. 1-13 2.1 Introduction..................................................................................................................... 2-1 2.1.1 Overview..................................................................................................................... 2-1 2.2 Signal Properties Summary ............................................................................................ 2-3 2.3 Signal Primary Functions................................................................................................ 2-7 2.3.1 Reset Signals............................................................................................................... 2-7 Freescale Semiconductor Contents Title Chapter 1 Overview Chapter 2 Signal Descriptions MCF5271 Reference Manual, Rev. 2 Page Number v ...
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... Additions to the Instruction Set Architecture ................................................................. 3-9 3.5 Exception Processing Overview ..................................................................................... 3-9 3.6 Exception Stack Frame Definition................................................................................ 3-11 3.7 Processor Exceptions .................................................................................................... 3-13 3.7.1 Access Error Exception ............................................................................................ 3-13 3.7.2 Address Error Exception........................................................................................... 3-13 vi Contents Title Chapter 3 ColdFire Core MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Fractional Operation Mode..................................................................................... 4-9 4.4.2 Mask Register (MASK) ............................................................................................ 4-11 4.5 EMAC Instruction Set Summary .................................................................................. 4-12 4.5.1 EMAC Instruction Execution Times ........................................................................ 4-13 4.5.2 Data Representation.................................................................................................. 4-14 4.5.3 MAC Opcodes .......................................................................................................... 4-14 Freescale Semiconductor Contents Title Chapter 4 MCF5271 Reference Manual, Rev. 2 Page Number vii ...
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... Normal PLL Mode with Crystal Reference............................................................ 7-5 7.1.3.2 Normal PLL Mode with External Reference.......................................................... 7-5 7.1.3.3 1:1 PLL Mode......................................................................................................... 7-5 7.1.3.4 External Clock Mode (Bypass Mode) .................................................................... 7-5 viii Contents Title Chapter 5 Cache Chapter 6 Static RAM (SRAM) Chapter 7 Clock Module MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Loss-of-Clock Interrupt Request .......................................................................... 7-26 7.4.6.12 Alternate Clock Selection ..................................................................................... 7-26 7.4.6.13 Loss-of-Clock in Stop Mode ................................................................................ 7-26 7.5 Interrupts ....................................................................................................................... 7-30 8.1 Introduction..................................................................................................................... 8-1 8.1.1 Features....................................................................................................................... 8-1 8.2 Memory Map/Register Definition .................................................................................. 8-1 Freescale Semiconductor Contents Title Chapter 8 Power Management MCF5271 Reference Manual, Rev. 2 Page Number ix ...
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... BDM ..................................................................................................................... 8-10 8.3.2.21 JTAG..................................................................................................................... 8-11 8.3.3 Summary of Peripheral State During Low-Power Modes ........................................ 8-11 Chip Configuration Module (CCM) 9.1 Introduction..................................................................................................................... 9-1 9.1.1 Block Diagram............................................................................................................ 9-1 9.1.2 Features....................................................................................................................... 9-1 9.1.3 Modes of Operation .................................................................................................... 9-2 x Contents Title Chapter 9 MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Power-On Reset .................................................................................................... 10-5 10.4.1.2 External Reset....................................................................................................... 10-5 10.4.1.3 Watchdog Timer Reset ......................................................................................... 10-5 10.4.1.4 Loss-of-Clock Reset ............................................................................................. 10-5 10.4.1.5 Loss-of-Lock Reset............................................................................................... 10-6 10.4.1.6 Software Reset ...................................................................................................... 10-6 10.4.2 Reset Control Flow ................................................................................................... 10-6 Freescale Semiconductor Contents Title Chapter 10 Reset Controller Module MCF5271 Reference Manual, Rev. 2 Page Number xi ...
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... Peripheral Access Control Registers (PACR0–PACR8).................................... 11-15 11.4.3.3 Grouped Peripheral Access Control Register (GPACR) .................................... 11-17 12.1 Introduction................................................................................................................... 12-1 12.1.1 Overview................................................................................................................... 12-3 12.1.2 Features..................................................................................................................... 12-3 xii Contents Title Chapter 11 System Control Module (SCM) Chapter 12 General Purpose I/O Module MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Interrupt Control Register (ICRx 2,..., 63)) ............................................ 13-12 13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)......... 13-14 13.3 Low-Power Wakeup Operation .................................................................................. 13-15 14.1 Introduction................................................................................................................... 14-1 14.1.1 Overview................................................................................................................... 14-1 Freescale Semiconductor Contents Title Chapter 13 Interrupt Controller Modules Chapter 14 DMA Controller Module MCF5271 Reference Manual, Rev. 2 Page ...
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... Edge Port Data Register (EPDR).......................................................................... 15-5 15.4.1.5 Edge Port Pin Data Register (EPPDR) ................................................................. 15-6 15.4.1.6 Edge Port Flag Register (EPFR)........................................................................... 15-6 16.1 Introduction................................................................................................................... 16-1 xiv Contents Title Chapter 15 Edge Port Module (EPORT) Chapter 16 Chip Select Module MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Line Transfers..................................................................................................... 17-12 17.5.7.2 Line Read Bus Cycles......................................................................................... 17-12 17.5.7.3 Line Write Bus Cycles........................................................................................ 17-14 17.6 Secondary Wait State Operation................................................................................. 17-15 17.7 Misaligned Operands .................................................................................................. 17-16 Freescale Semiconductor Contents Title Chapter 17 External Interface Module (EIM) MCF5271 Reference Manual, Rev. 2 Page Number xv ...
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... Full and Half Duplex Operation ........................................................................... 19-4 19.1.5 Interface Options....................................................................................................... 19-4 19.1.5.1 10 Mbps and 100 Mbps MII Interface.................................................................. 19-4 19.1.5.2 10 Mpbs 7-Wire Interface Operation.................................................................... 19-5 xvi Contents Title Chapter 18 Chapter 19 Fast Ethernet Controller (FEC) MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Initialization Sequence............................................................................................ 19-35 19.3.1.1 Hardware Controlled Initialization ..................................................................... 19-35 19.3.2 User Initialization (Prior to Setting ECR[ETHER_EN])........................................ 19-35 19.3.3 Microcontroller Initialization.................................................................................. 19-36 19.3.4 User Initialization (After Asserting ECR[ETHER_EN]) ....................................... 19-37 19.3.5 Network Interface Options...................................................................................... 19-37 Freescale Semiconductor Contents Title MCF5271 Reference Manual, Rev. 2 Page Number xvii ...
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... PIT Modulus Register (PMRn)............................................................................. 21-5 21.2.1.3 PIT Count Register (PCNTRn)............................................................................. 21-5 21.3 Functional Description.................................................................................................. 21-6 21.3.1 Set-and-Forget Timer Operation............................................................................... 21-6 21.3.2 Free-Running Timer Operation ................................................................................ 21-6 xviii Contents Title Chapter 20 Watchdog Timer Module Chapter 21 MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Operation ...................................................................................................................... 23-3 23.2.1 QSPI RAM................................................................................................................ 23-4 23.2.1.1 Receive RAM ....................................................................................................... 23-5 23.2.1.2 Transmit RAM...................................................................................................... 23-5 23.2.1.3 Command RAM.................................................................................................... 23-6 23.2.2 Baud Rate Selection.................................................................................................. 23-6 Freescale Semiconductor Contents Title Chapter 22 DMA Timers (DTIM0–DTIM3) Chapter 23 MCF5271 Reference Manual, Rev. 2 Page Number xix ...
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... Functional Description................................................................................................ 24-17 24.4.1 Transmitter/Receiver Clock Source........................................................................ 24-17 24.4.1.1 Programmable Divider........................................................................................ 24-17 24.4.1.2 Calculating Baud Rates....................................................................................... 24-18 24.4.2 Transmitter and Receiver Operating Modes........................................................... 24-19 24.4.2.1 Transmitter.......................................................................................................... 24-19 24.4.2.2 Receiver .............................................................................................................. 24-21 xx Contents Title Chapter 24 UART Modules MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... C Programming Examples ....................................................................................... 25-13 25.6.1 Initialization Sequence............................................................................................ 25-13 25.6.2 Generation of START............................................................................................. 25-14 25.6.3 Post-Transfer Software Response........................................................................... 25-14 25.6.4 Generation of STOP................................................................................................ 25-15 25.6.5 Generation of Repeated START............................................................................. 25-16 25.6.6 Slave Mode ............................................................................................................. 25-16 Freescale Semiconductor Contents Title Chapter Interface MCF5271 Reference Manual, Rev. 2 Page Number xxi ...
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... Generation of Key with IPAD ............................................................................ 26-16 26.4.2.2 Generation of Key with OPAD........................................................................... 26-16 26.4.2.3 HMAC Hash ....................................................................................................... 26-17 26.4.3 Performing a SHA-1 EHMAC................................................................................ 26-17 26.4.4 Performing a MAC Operation With the MACFULL Bit ....................................... 26-18 26.4.5 Performing an NMAC ............................................................................................ 26-19 xxii Contents Title Chapter 26 MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... SKHA Key Size Register (SKKSR) ................................................................... 28-13 28.2.1.8 SKHA Data Size Register (SKDSR) .................................................................. 28-13 28.2.1.9 SKHA Input FIFO .............................................................................................. 28-14 28.2.1.10 SKHA Output FIFO........................................................................................... 28-14 28.2.1.11 SKHA Key Data Registers (SKKDRn) ............................................................. 28-14 Freescale Semiconductor Contents Title Chapter 27 Chapter 28 MCF5271 Reference Manual, Rev. 2 Page Number xxiii ...
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... Boundary Scan Register ....................................................................................... 29-6 29.4 Functional Description.................................................................................................. 29-7 29.4.1 JTAG Module ........................................................................................................... 29-7 29.4.2 TAP Controller ......................................................................................................... 29-7 29.4.3 JTAG Instructions..................................................................................................... 29-8 29.4.3.1 EXTEST Instruction ............................................................................................. 29-9 29.4.3.2 IDCODE Instruction............................................................................................. 29-9 xxiv Contents Title Chapter 29 MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Emulator Mode ................................................................................................... 30-39 30.6.2 Concurrent BDM and Processor Operation ............................................................ 30-39 30.7 Processor Status, DDATA Definition......................................................................... 30-40 30.7.1 User Instruction Set ................................................................................................ 30-40 30.7.2 Supervisor Instruction Set....................................................................................... 30-44 Freescale Semiconductor Contents Title Chapter 30 Debug Support MCF5271 Reference Manual, Rev. 2 Page Number xxv ...
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... Paragraph Number 30.8 Freescale-Recommended BDM Pinout ...................................................................... 30-45 Register Memory Map Quick Reference A.1 Register Memory Map .................................................................................................... 1-1 xxvi Contents Title Appendix A MCF5271 Reference Manual, Rev. 2 Page Number Freescale Semiconductor ...
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... Chapter 4, “Enhanced Multiply-Accumulate Unit multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The EMAC is integrated into the operand execution pipeline (OEP). Freescale Semiconductor ® architecture. Core,” provides an overview of the microprocessor core of the (EMAC),” describes the MCF5271 MCF5271 Reference Manual, Rev. 2 Section 1.1, “ ...
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... Modules,” describes operation of the interrupt controller Module,” describes the MCF5271 Direct Memory Access (EPORT),” describes EPORT module functionality, Module,” describes the MCF5271 chip-select implementation, (EIM),” describes data-transfer operations, error Module,” describes the configuration and MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... IEEE 1149.1 standard and provides additional information specific to the MCF5271. For internal details and sample applications, see the IEEE 1149.1 document. Freescale Semiconductor (FEC),” provides a feature-set overview, a functional Module,” describes Watchdog timer functionality, including (PIT0–PIT3),” describes the (DTIM0– ...
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... Also, if mistakes are found within a reference manual, an errata document will be issued before the next published release of the reference manual. These addenda/errata are intended for use with the corresponding reference manuals. xxx Reference,” provides the entire address-map MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... This document is roughly equivalent to the overview (Chapter implementation’s reference manual. • Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of ColdFire documentation, refer to http://www.freescale.com/coldfire. ...
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... Least-significant byte lsb Least-significant bit MAC Multiply accumulate unit, also Media access controller MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter xxxii Meaning MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... Source and destination address registers, respectively Dn Any data register n (example data register 5) Dy,Dx Source and destination data registers, respectively Rc Any control register (example VBR is the vector base register) Freescale Semiconductor Meaning Table ii. Notational Conventions Operand Syntax Opcode Wildcard Register Specifications MCF5271 Reference Manual, Rev. 2 ...
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... Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) xxxiv Operand Syntax Register Names Port Name Miscellaneous Operands MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... Least significant bit (example: lsb of D0) LSB Least significant byte LSW Least significant word msb Most significant bit MSB Most significant byte MSW Most significant word Freescale Semiconductor Operand Syntax Operations Subfields and Qualifiers is a 16-bit displacement) 16 MCF5271 Reference Manual, Rev. 2 Terminology Conventions xxxv ...
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... Changes are noted in revision 1.3 or later of the MCF5271RMAD document. — Changes are noted in revision 1.6 or later of the MCF5271RMAD document. xxxvi Operand Syntax Condition Code Register Bit Names Substantive Changes Revision 0, 04/26/2004 Revision 1.0, 08/16/2004 Revision 1.1, 04/2005 Revision 2, 07/2006 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... Performance (Dhrystone/2.1 MIPS) Instruction/Data Cache Static RAM (SRAM) Interrupt Controllers (INTC) Edge Port Module (EPORT) External Interface Module (EIM) 4-channel Direct-Memory Access (DMA) SDRAM Controller Fast Ethernet Controller (FEC) Cryptography Hardware Accelerators Freescale Semiconductor Module 5270 150 MHz up to 144 8 Kbytes 64 Kbytes ...
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... The superset device in the MCF5271 family comes in a 196 mold array process ball grid array (MAPBGA) package. Figure 1-1 1-2 Module 5270 160 QFP 196 MAPBGA shows a top-level block diagram of the MCF5271. MCF5271 Reference Manual, Rev. 2 5271 160 QFP 196 MAPBGA Freescale Semiconductor ...
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... FAST ETHERNET (To/From PADI) CONTROLLER (FEC) (To/From PADI DMA (To/From PADI) DREQ[2:0] DACK[2:0] JTAG_EN JTAG TAP Watchdog Timer SKHA RNGA MDHA Cryptography Modules Freescale Semiconductor (To/From SRAM backdoor) INTC0 INTC1 Arbiter UART UART UART DTIM DTIM DTIM ColdFire CPU EMAC DIV ...
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... Built-in dedicated DMA controller — Memory-based flexible descriptor rings — Media independent interface (MII) to external transceiver (PHY) • Three Universal Asynchronous Receiver Transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic — Maskable interrupts 1-4 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... DMA trigger capability on input capture or reference-compare • Four Periodic Interrupt Timers (PITs) — 16-bit counter — Selectable as free running or count down • Software Watchdog Timer — 16-bit counter — Low power mode support Freescale Semiconductor C bus 2 MCF5271 Reference Manual, Rev. 2 Features 1-5 ...
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... Support for n-1-1-1 burst fetches from page mode Flash — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator — 32-bit bidirectional data bus — 24-bit address bus — eight chip selects available 1-6 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... The EMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Features 1-7 ...
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... Bypass the MCF5271 for a given circuit board test by effectively reducing the boundary-scan register to a single bit • Disable the output drive to pins during circuit-board testing • Drive output pins to stable levels 1-8 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... CSMA/CD media access control and channel interface functions. The FEC supports connection and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external transceiver (PHY) to complete the interface to the media. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Features 1-9 ...
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... The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at regular intervals with minimal processor intervention. Each timer can either count down from the value written in its PIT modulus register can be a free-running down-counter. 1-10 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... Base memory address and block size are programmable, with some restrictions. For example, the starting address must boundary that is a multiple of the block size. Each chip select can be configured to provide read and write enable signals suitable for use with most popular static RAMs Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Features ...
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... In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported. The digital I/O pins on the MCF5271 are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins. 1-12 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... Documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Documentation 1-13 ...
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... Overview 1-14 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... The term ‘negated’ indicates that a signal is inactive. Active-low signals, such as SD_SRAS and TA, are indicated with an overbar. 2.1.1 Overview Figure 2-1 shows the block diagram of the MCF5271 with the signal interface. Freescale Semiconductor Chapter 17, “External Interface Module NOTE MCF5271 Reference Manual, Rev. 2 (EIM),” describes how 2-1 ...
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... MCF5271 Reference Manual, Rev. 2 TDO/DSO TCLK/PSTCLK TMS/BKPT JTAG TDI/DSI Port TRST/DSCLK JTAG_EN Controller Debug Module DDATA[3:0] 4 ColdFire V2 Core 64K SRAM DIV EMAC 8-Kbyte D-Cache/I-Cache DMA Timer Watchdog Modules Timer Module (DTIM0– DTIM3) Prog. Interrupt Timers (PIT0– PIT3) Freescale Semiconductor Test ...
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... Table 2-1. MCF5270 and MCF5271 Signal Information and Muxing Signal Name GPIO RESET — RSTOUT — EXTAL — XTAL — CLKOUT — CLKMOD[1:0 — ] RCON — A[23:21] PADDR[7:5] A[20:0] — Freescale Semiconductor NOTE NOTE MCF5270 Alternate Alternate Dir. MCF5271 160 QFP Reset — — I — — O Clock — — ...
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... K3, K4, L1, L2 42:49 M1, N1, M2, N2, P2, L3, M3, N3 P3, M4, N4, P4, L5, M5, N5, P5 B6, C6, D7 H11 — J14 95 J13 — P6 — H13 — H12 — B9, A10, C10, A11 A9, C9 130 B10 129 D10 92 K13 91 K12 90 K11 139 E8 — L12, L13 N7, M7, L7, P8, N8 Freescale Semiconductor ...
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... TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1, TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for DREQ2, TEA and DT1IN for DREQ1, and TIP and DT0IN QSPI_CS1 PQSPI4 QSPI_CS0 PQSPI3 QSPI_CLK PQSPI2 QSPI_DIN PQSPI1 QSPI_DOUT PQSPI0 Freescale Semiconductor Alternate Alternate Dir DREQ2 — I — — I ...
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... O — — O MCF5271 Reference Manual, Rev. 2 MCF5270 MCF5271 196 MAPBGA — A8 — A7 136 B8 135 C8 133 D9 134 — H14 — G14 66 M9 — — P10 73 M10 72 N10 78 K9 — M12, N12, P12, L11 77:74 M11, N11, P11, L10 Freescale Semiconductor ...
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... Signal Primary Functions 2.3.1 Reset Signals Table 2-2 describes signals that are used to either reset the chip reset indication. Signal Name Abbreviation Reset In RESET Reset Out RSTOUT Freescale Semiconductor MCF5270 Alternate Alternate Dir. MCF5271 160 QFP Test — ...
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... SDRAM controller row and column addresses. These three-state bidirectional signals provide the general purpose data path between the processor and all other devices. The D[15:0] pins can be configured as GPIO when using a 16-bit bus. MCF5271 Reference Manual, Rev sys/2 I I/O O I/O Freescale Semiconductor ...
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... CS[7:0] 2.3.5 SDRAM Controller Signals Table 2-6 describes signals that are used for SDRAM accesses. Freescale Semiconductor Function Define the flow of data on the data bus. During SRAM and peripheral accesses, these output signals indicate that data latched or driven onto a byte of the data when driven low. The BS[3:0] signals are asserted only to the memory bytes used during a read or write access ...
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... ETXEN. This signal is used for 10-Mbps Ethernet data also used for MII mode data in conjunction with ETXD[3:1]. Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. MCF5271 Reference Manual, Rev I/O I I/O I Freescale Semiconductor ...
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... I2C_SDA 2.3.9 Queued Serial Peripheral Interface (QSPI) Table 2-10 describes QSPI signals. Freescale Semiconductor Function Provides a timing reference for ERXDV, ERXD[3:0], and ERXER. Asserting the receive data valid (ERXDV) input indicates that the PHY has valid nibbles present on the MII. ERXDV should remain asserted from the first recovered nibble of the frame through to the last nibble ...
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... When the UART clock is stopped for power-down mode, any transition on this pin restarts it. U1RTS/U0RTS can also be configured to be asserted and negated as a function of the RxFIFO level. MCF5271 Reference Manual, Rev. 2 ÷ (2 × n) sys/2 Freescale Semiconductor I I/O O ...
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... Clock Breakpoint BKPT Development Serial DSI Input Freescale Semiconductor Table 2-12. DMA Timer Signals Function Can be programmed to cause events to occur in first platform timer. It can either clock the event counter or provide a trigger to the timer value capture logic. The output from first platform timer. ...
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... Begin execution of taken branch Reserved Begin execution of RTE instruction Begin one-byte transfer on DDATA Begin two-byte transfer on DDATA Begin three-byte transfer on DDATA Begin four-byte transfer on DDATA Exception processing Reserved Processor is stopped Processor is halted MCF5271 Reference Manual, Rev 2-14. Debug mode timing Freescale Semiconductor ...
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... D[31:0] BS[3: TEA R/W TSIZ[1:0] Freescale Semiconductor Table 2-15. Test Signals Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions. Reserved for factory testing only and should be treated as a no-connect (NC). provide system power and ground to the chip. Multiple pins are Table 2-16 ...
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... Signal Descriptions Table 2-17. Default Signal Functions After System Reset (External Boot Mode) (Contin- Signal TS TIP CS[7:0] 2-16 Reset High High High MCF5271 Reference Manual, Rev Freescale Semiconductor ...
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... The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The Instruction Fetch Pipeline (IFP two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage Operand Execution Pipeline (OEP), Freescale Semiconductor Instruction Address Generation ...
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... Data Registers (D0–D7) Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers. 3-2 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... The PC contains the address of the currently executing instruction. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. For some addressing modes, the PC is used as a base address for PC-relative operand addressing. 31 Figure 3-2. User Programming Model Freescale Semiconductor OTHER_A7).” ...
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... Carry condition code bit. Set if a carry out of the operand msb occurs for an addition borrow occurs in a subtraction; otherwise cleared Set to the value of the C bit for arithmetic operations; otherwise not affected. (EMAC),” and include the following registers: MCF5271 Reference Manual, Rev Chapter 4, Freescale Semiconductor ...
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... Two 32-bit access control registers (ACR0, ACR1) • Two 32-bit base address registers (RAMBAR) Table 3-3. Supervisor Programming Model 31:24 — Freescale Semiconductor Table 3-2. Table 3-2. EMAC Register Set 23:16 15:8 MAC Status Register ...
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... CCR Refer to 3-6 23:16 15:8 Access Control Register 1 RAM Base Address Register — I — CPU @ 0x80E Figure 3-4. Status Register (SR) Table 3-4. SR Field Descriptions Description Table 3-1. MCF5271 Reference Manual, Rev. 2 7:0 Mnemonic ACR1 RAMBAR1 Condition Code Register (CCR Freescale Semiconductor ...
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... The CACR controls operation of the instruction/data cache memories. It includes bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and write-protect fields. The CACR is described in (CACR).” Freescale Semiconductor Section 5.2.1.1, “Cache Control Register MCF5271 Reference Manual, Rev. 2 Processor Register Description the supervisor — ...
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... MAC status register 0x805 No MAC address mask register No MAC accumulators 0-3 0x807 No MAC accumulator 0, 1 extension bytes 0x808 No MAC accumulator 2, 3 extension bytes 0x80E No Status register 0x80F Yes Program counter MCF5271 Reference Manual, Rev. 2 ACR1).” Section 6.2.1, Register Name Freescale Semiconductor ...
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... M68000 family in that they include: • A simplified exception vector table • Reduced relocation capabilities using the vector base register • A single exception stack frame format • Use of a single self-aligning system stack Freescale Semiconductor Written with MOVEC Local Memory Registers 0xC05 ...
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... Freescale and the remaining 192 are user-defined interrupt vectors. Table 3-7. Exception Vector Assignments Vector Number( 3-10 Exception” for details. Stacked Vector Program Offset (Hex) Counter 0x000 — 0x004 — 0x008 Fault MCF5271 Reference Manual, Rev. 2 Assignment Initial stack pointer Initial program counter Access error Freescale Semiconductor ...
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... Section 3.14, “ColdFire Instruction Set Architecture 3.6 Exception Stack Frame Definition The exception stack frame is shown in contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the second longword contains the 32-bit program counter address. Freescale Semiconductor Stacked Vector Program Offset (Hex) Counter ...
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... Original SSP - 11 Table 3-9. Fault Status Encodings Definition Reserved Error on instruction fetch Reserved Reserved Error on operand write Attempted write to write-protected space Reserved Error on operand read Reserved Reserved Table 3-7. MCF5271 Reference Manual, Rev Status Register Table 3-8. Format Field Freescale Semiconductor ...
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... Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and most line-F opcode generates their unique exception types, vector numbers Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Processor Exceptions ...
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... TRAP exception handler to check for this condition (SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception. 3-14 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from the interrupt controller using an IACK cycle. See Modules,” for details on the interrupt controller. Freescale Semiconductor Chapter 32, “Debug Support.” MCF5271 Reference Manual, Rev. 2 Processor Exceptions Chapter 13, “Interrupt Controller ...
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... The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via BDM to determine the hardware configuration. Information loaded into D0 defines the processor hardware configuration as shown in 3-16 NOTE MCF5271 Reference Manual, Rev. 2 Figure 3-6. Freescale Semiconductor ...
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... FPU execute engine not present in core. (This is the value used for MCF5271) 1 FPU execute engine is present in core. 11 MMU Virtual memory management unit status. 0 MMU execute engine not present in core. (This is the value used for MCF5271) 1 MMU execute engine is present in core. 10–8 — Reserved. Freescale Semiconductor ...
Page 84
... All other values do not apply for MCF5271 23–16 — Reserved for MCF5271 15–14 BUSW Encoded bus data width. 00 32-bit data bus (only configuration currently in use). 3-18 Description instructions. This is the value used for MCF5271 ICSIZ DCSIZ Description MCF5271 Reference Manual, Rev — RAM1SIZ ROM1SIZ Freescale Semiconductor ...
Page 85
... STORE instruction is encountered within this 2-cycle window, it will be stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive STORE operations is 2 cycles. The MOVEM instruction uses a different set of resources and this stall does not apply. Freescale Semiconductor Description MCF5271 Reference Manual, Rev. 2 Instruction Execution Timing ...
Page 86
... Table 3-13, while Table 3-14 (d ,Ax) (d ,Ax,Xi) (xxx). 1(0/1) 2(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) 3(1/1) 4(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) 3(1/1) — — — — — — — — Freescale Semiconductor ...
Page 87
... Standard One Operand Instruction Execution Times Table 3-15. One Operand Instruction Execution Times Opcode <EA> Rn bitrev Dx 1(0/0) byterev Dx 1(0/0) clr.b <ea> 1(0/0) clr.w <ea> 1(0/0) clr.l <ea> 1(0/0) Freescale Semiconductor Destination (Ax) (Ax)+ -(Ax) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 4(1/1) 4(1/1) 3(0/1) 3(0/1) 3(0/1) Destination (Ax) (Ax)+ ...
Page 88
... Freescale Semiconductor #xxx — — — — — — — — 5(0/1) — 1(0/0) 1(0/0) 1(0/0) #xxx — — — — ...
Page 89
... Dy,Dx 1(0/0) 1 For divide and remainder instructions the times listed represent the worst-case timing. Depending on the operand values, the actual execution time may be less. Freescale Semiconductor Standard Two Operand Instruction Execution Times Effective Address (d16,An) (An) (An)+ -(An) (d16,PC) ...
Page 90
... Freescale Semiconductor #xxx — — 1(0/0) — 2 7(0/0) — — — — — — 3 3(0/0) 15(1/2) — — — — ...
Page 91
... Rmask, <ea>x mov.l Raccext01,<ea.x mov.l Raccext23,<ea>x 1 Effective address of (d16,PC) not supported 2 Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] = 1---, -11-, --11) Freescale Semiconductor Effective Address Rn (An) (An)+ -(An) 4(0/0) 6(1/0) 6(1/0) 6(1/0) 4(0/0) ...
Page 92
... Not Taken 2(0/0) — 3(0/0) 1(0/0) MCF5271 Reference Manual, Rev. 2 (d8,An,Xi*SF) xxx.wl (d8,PC,Xi*SF) — — 4(0/0) 3(0/0) 4(0/1) 3(0/1) — — — — — — Backward Taken Not Taken 2(0/0) — 2(0/0) 3(0/0) Freescale Semiconductor #xxx — — — — — ...
Page 93
... The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0], new Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31]. Condition Codes: Not affected Instruction Field: • Register field—Specifies the destination data register, Dx. BITREV Opcode present Freescale Semiconductor Bit Reverse Register (Supported Starting with ISA A ...
Page 94
... Opcode present 3-28 Byte Reverse Register (Supported Starting with ISA A new Dx[31:24] = old Dx[7:0] new Dx[23:16] = old Dx[15:8] new Dx[15:8] = old Dx[23:16] new Dx[7:0] = old Dx[31:24] V2, V3 Core (ISA_A) V4 Core (ISA_B) No MCF5271 Reference Manual, Rev. 2 BYTEREV Register Core (ISA_A+) No Yes Freescale Semiconductor 0 ...
Page 95
... If the source data is zero, then an offset returned. Condition ∗ ∗ Codes: — Instruction Field: • Destination Register field—Specifies the destination data register, Dx. FF1 Opcode present Freescale Semiconductor ColdFire Instruction Set Architecture Enhancements Find First One in Register (Supported Starting with ISA A ...
Page 96
... Z Set to the value of bit 2 of the immediate operand V Set to the value of bit 1 of the immediate operand C Set to the value of bit 0 of the immediate operand V2, V3 Core (ISA_A) V4 Core (ISA_B) No MCF5271 Reference Manual, Rev. 2 STRLDSR Core (ISA_A+) No Yes Freescale Semiconductor ...
Page 97
... The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module, as shown in Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Figure 4-1. 4-1 ...
Page 98
... To show this point, reduce the above equation to a simple, four-tap FIR filter, shown in data values and coefficients. 4-2 Operand Y Operand X X Shift 0,1,- Accumulator( – – ∑ ∑ – Figure 4-3, in which the accumulated sum is a sum of past MCF5271 Reference Manual, Rev. 2 Figure 4- – Freescale Semiconductor ...
Page 99
... Figure 4-4 and Figure 4-5 show relative alignment of input operands, the full 64-bit product, the resulting 40-bit product used for accumulation, and 48-bit accumulator formats. Freescale Semiconductor ( ) – ...
Page 100
... ACCn contents, the specific definitions are as follows: if MACSR[6:5] == 00/* signed integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} 4-4 32 OperandY X OperandX Accumulator [31:0] Figure 4-4. Fractional Alignment OperandY X OperandX Extension Byte Lower [7:0] MCF5271 Reference Manual, Rev “0” 8 Extension Byte Lower [7: Accumulator [31:0] Freescale Semiconductor ...
Page 101
... Operational mode bits control whether operands are signed or unsigned and whether they are treated as integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding is performed. Negative, zero, and multiple overflow condition flags are also provided. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 General Operation 4-5 ...
Page 102
... ACCext01 Extensions for ACC0 and ACC1 ACCext23 Extensions for ACC2 and ACC3 MASK MAC mask register Figure 4-6. EMAC Register Set 12 11–8 Prod/acc overflow flags PAVx OM 0000_0000_0000_0000_0000_0000_0000_0000 R/W MCF5271 Reference Manual, Rev Operational Mode Flags S/U F/I R Freescale Semiconductor 0 EV ...
Page 103
... Integers can be represented in either signed or unsigned notation, depending on the value of S/U. 1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from - Section 4.5.2, “Data Freescale Semiconductor Description Operational Mode Fields -15 for 16-bit fractions and - Representation." MCF5271 Reference Manual, Rev. 2 Memory Map/Register Definition Section 4 ...
Page 104
... Although an overflow has occurred, the correct result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent MAC or MSAC operations may return the accumulator to a valid 32/40-bit result. Table 4-2 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits. 4-8 Description Flags MCF5271 Reference Manual, Rev. 2 Section 4.4.1.1.1, Freescale Semiconductor ...
Page 105
... If R0.L is greater than 0x8000, the upper word is incremented (rounded up). • If R0.L is 0x8000 half-way between two 16-bit numbers. In this case, rounding is based on the lsb of R0.U, so the result is always even (lsb = 0). — If the lsb of R0 and R0.L = 0x8000, the number is rounded up. Freescale Semiconductor Operational Modes 0 x ...
Page 106
... The following code performs the EMAC state restore: 4-10 then Result = R0.U else Result = R0 save the macsr ; zero the register to ... ; disable rounding in the macsr ; save the accumulators ; save the accumulator extensions ; save the address mask ; move the state to memory MCF5271 Reference Manual, Rev R0.L = 0x8000 */ Freescale Semiconductor ...
Page 107
... Ry,RxSF,<ea>y&,Rw The & operator enables the use of MASK and causes bit 5 of the extension word to be set. The exact algorithm for the use of MASK is as follows: Freescale Semiconductor ; restore the state from memory ; disable rounding in the macsr ; restore the accumulators ...
Page 108
... Write the contents of MACSR to a CPU register Write the contents of MACSR to the CCR Writes a value to the MASK register Writes the contents of the MASK to a CPU register Loads the accumulator 0,1 extension bytes with a 32-bit operand MCF5271 Reference Manual, Rev. 2 Description Freescale Semiconductor ...
Page 109
... EMAC EX1 EMAC EX2 EMAC EX3 EMAC EX4 Accumulator 0 Figure 4-8. EMAC-Specific OEP Sequence Stall Freescale Semiconductor Mnemonic Loads the accumulator 2,3 extension bytes with a 32-bit operand Writes the contents of accumulator 0,1 extension bytes into a CPU register Writes the contents of accumulator 2,3 extension bytes into a ...
Page 110
... Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that involves the product and the accumulator. 4- The binary point is right of the lsb. , its value is given by the equation – ∑ ( ⋅ – – MCF5271 Reference Manual, Rev. 2 Figure 4- – ⋅ ai (N-1) . -31 ). Freescale Semiconductor N ...
Page 111
... Ry[31], Ry[31:16]} else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]} if (U/ then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]} Freescale Semiconductor Section 4.4.1, “MAC Status Register MCF5271 Reference Manual, Rev. 2 EMAC Instruction Set Summary (MACSR).” 4-15 ...
Page 112
... MAC, saturationMode enabled */ if (product[63 then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<< 1” reserved encoding */ /* SF = “>> 1” */ then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0] MCF5271 Reference Manual, Rev sign-extend */ Freescale Semiconductor ...
Page 113
... MSAC) then result[47:0] = ACCx[47:0] - product[71:24] else result[47:0] = ACCx[47:0] + product[71:24] Freescale Semiconductor then /* accumulation overflow, saturationMode enabled */ if (result[47 then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 /* signed fractionals */ ...
Page 114
... Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} then operandX[31:0] = {0x0000, Rx[31:16]} else operandX[31:0] = {0x0000, Rx[15:0]} /* product overflow */ then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 115
... MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR else MACSR (ACCx[47:32] == 0x0000) then MACSR. else MACSR. break; } Freescale Semiconductor result[47:0] = 0xffff_ffff_ffff /* zero-fill upper byte */ /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<< 1” reserved encoding */ /* SF = “>> 1” */ then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0] then result[47:0] = 0x0000_0000_0000 else if (MACSR ...
Page 116
... Enhanced Multiply-Accumulate Unit (EMAC) 4-20 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 117
... This address field is compared to bits [31:13] for instruction- or data-only configurations and to bits [31:12] for a split configuration of the fetch address from the local bus to determine if a cache hit has occurred. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 5-1 ...
Page 118
... The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is released after the initial access of a miss. Thus, the cache or the SRAM module can service subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer. 5-2 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 119
... If the referenced address is mapped into the SRAM module, that module will service the request in a single cycle. In this case, data accessed from the cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the cache handles the request in the normal fashion. Freescale Semiconductor ...
Page 120
... CACR[CPDI] is cleared. For the split data/instruction cache configuration, software directly controls bit 12 which selects whether an instruction cache or data cache line is being accessed. These invalidation operations can be initiated from the ColdFire core or the debug module. 5-4 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 121
... Once an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache maintains a special “most-recently-used” indicator that tracks the contents of the associated Freescale Semiconductor Organization,” the cache hardware includes a 16-byte Longword Address Bits ...
Page 122
... Noncacheable Instruction fetch size is defined by loaded into the line-fill buffer, but are never written into the memory array. MCF5271 Reference Manual, Rev. 2 Description Table 5-1 and contents of the Table 5-1 and Table 5-3 below shows Freescale Semiconductor ...
Page 123
... At system reset, the entire register is cleared CENB — CPD CFRZ Reset — Reset Address Figure 5-2. Cache Control Register (CACR) Freescale Semiconductor Name Width Description CACR 32 Cache Control Register ACR0 32 Access Control Register 0 ACR1 32 Access Control Register — CINV DISI DISD INVI INVD ...
Page 124
... Table 5-4. CACR Field Descriptions Description describes cache configuration. describes how to set the cache invalidate all bit. describes cache configuration and describes cache configuration and MCF5271 Reference Manual, Rev. 2 Table 5-6 describes how to set the cache Table 5-6 describes how to set the cache Freescale Semiconductor ...
Page 125
... Cache line fill. These bits control the size of the memory request the cache issues to the bus controller for different initial instruction line access offsets. See fetch size based on miss address and CLNF. Freescale Semiconductor Description describes how to set the cache invalidate all bit. ...
Page 126
... Invalidate only 4 KByte data cache Data Cache 0 Split Instruction Invalidate only 4 KByte instruction cache Data Cache 1 Split Instruction/ No invalidate Data Cache x Instruction Cache Invalidate 8 KByte instruction cache x Data Cache Invalidate 8 KByte data cache MCF5271 Reference Manual, Rev. 2 Description Operation Freescale Semiconductor ...
Page 127
... ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all accesses. 00 Match if user mode 01 Match if supervisor mode 1x Match always—ignore user/supervisor mode 12–7 — Reserved, should be cleared Cache mode. This bit defines the cache mode cacheable noncacheable. 0 Caching enabled 1 Caching disabled Freescale Semiconductor NOTE ...
Page 128
... Write protect. The WP bit defines the write-protection attribute. If the effective memory attributes for a given access select the WP bit, an access error terminates any attempted write with this bit set. 0 Read and write accesses permitted 1 Only read accesses permitted 1–0 — Reserved, should be cleared. 5-12 Description MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 129
... See Section 11.3, “Internal Bus Arbitration,” 6.2 Register Description The SRAM programming model includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 for more information. 6-1 ...
Page 130
... See Note BA — — — — — — See Note PRI1 PRI0 SPV — — — — — — CPU + 0x0C05 Description MCF5271 Reference Manual, Rev. 2 Figure 6- — — — — — — C — — — — — 0 Freescale Semiconductor ...
Page 131
... These bits are useful for power management as detailed in Management.” Valid. A hardware reset clears this bit. When set, this bit enables the SRAM module; otherwise, the module is disabled. 0 Contents of RAMBAR are not valid 1 Contents of RAMBAR are valid Freescale Semiconductor Description PRI[1:0] Upper Bank Priority 00 CPU Accesses 01 CPU Accesses ...
Page 132
... SRAM_INIT_LOOP 6-4 ;set this variable to $20000000 ;load RAMBASE + valid bit into D0. ;load RAMBAR and enable SRAM ;load pointer to SRAM ;load loop counter into D0 ;clear 4 bytes of SRAM ;decrement loop counter ;if done, then exit; else continue looping MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 133
... Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power dissipation. RAMBAR settings. Table 6-2. Typical RAMBAR Setting Examples Data Contained in SRAM Both Instructions And Data Freescale Semiconductor Table 6-2 RAMBAR[7:0] Instruction Only Data Only MCF5271 Reference Manual, Rev. 2 ...
Page 134
... Static RAM (SRAM) 6-6 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 135
... Frequency Modulated Phase-locked loop (PLL) • Reduced frequency divider (RFD) • Status and control registers • Control logic Throughout this manual, f refers to the internal bus frequency. Freescale Semiconductor NOTE refers to the core frequency and f sys MCF5271 Reference Manual, Rev. 2 sys/2 ...
Page 136
... The PLL block in this diagram is expanded in detail in Figure 7-2 1 PLLMODE 1 f sys 0 0 PLLSEL Clock Module 7-3. MCF5271 Reference Manual, Rev. 2 ColdFire V2 Core BDM DMA ÷ 2 SDRAMC EIM Chip Selects Watchdog PIT DMA Timers QSPI UART RNG MDHA SKHA FEC GPIO Freescale Semiconductor ...
Page 137
... EXTAL XTAL External Clock OSC STPMD Stop Mode Figure 7-2. Clock Module Block Diagram Freescale Semiconductor CLKMOD[1:0] RSTOUT MFD PLLMODE Reference Clock PLL PLLREF LOCEN LOLRE CLKGEN PLLSEL DISCLK PLLMODE MCF5271 Reference Manual, Rev. 2 CLKOUT LOCKS LOCK LOCS RFD[2:0] To Reset Module ...
Page 138
... PLL mode, or external clock mode. 7-4 Successive Approximation Frequency Search PFD/ Filter Charge Pumps MFD Control/Status Registers Figure 7-3. PLL Block Diagram for valid states of CLKMOD[1:0]. If CLKMOD[1:0] are not asserted MCF5271 Reference Manual, Rev Control PLL OUT ICO Freescale Semiconductor ...
Page 139
... EXTAL pin. The external clock is used directly to produce the internal core clocks. Refer to the Hardware Specification document for external clock input requirements. In external clock mode, the analog portion of the PLL is disabled and no clocks are generated at the PLL Freescale Semiconductor =2×f and f ...
Page 140
... Internal bus clock output MCF5271 Reference Manual, Rev. 2 Management.” Table 7-1 Mode Exit clocking resumes upon mode exit clocking resumes upon mode exit Exit not caused by clock module, but clock sources are re-enabled and normal clocking resumes upon mode exit Freescale Semiconductor shows ...
Page 141
... The RSTOUT pin is asserted by one of the following: • Internal system reset signal • FRCRSTOUT bit in the reset control status register (RCR); see Control Register (RCR).” Freescale Semiconductor Function Clock mode select inputs Reset signal from reset controller Table 7-3. Clock Mode Selection ...
Page 142
... R DISCLK LOLIRQ LOCIRQ RATE W Reset Address Figure 7-4. Synthesizer Control Register (SYNCR) 7-8 Register Name Synthesizer Control Register (SYNCR) Synthesizer Status Register (SYNSR MFD[2:0] — DEPTH IPSBAR + 0x0012_0000 MCF5271 Reference Manual, Rev Access RFD[2:0] LOCEN LOLRE LOCRE EXP[9: Freescale Semiconductor ...
Page 143
... When operation in normal or 1:1 mode, the PLL must be locked before setting the LOLRE bit. Otherwise reset is immediately asserted. 0 Ignore loss-of-clock – no reset 1 Reset on loss-of-lock Note: In external clock mode, the LOLRE bit has no effect Freescale Semiconductor Table 7-5. SYNCR Field Descriptions Description 1 in normal PLL mode. ...
Page 144
... Entering FM calibration mode requires the user to program the EXP field. 7-10 Description = ref = ref ) = 0 sys 1.0 ± 0.2 sys 2.0 ± 0.2 sys/2 Section 7.4.5, “Frequency Modulation Depth Calibration,” MCF5271 Reference Manual, Rev. 2 for details on how Freescale Semiconductor ...
Page 145
... A loss-of-clock condition can only be detected if LOCEN = 1. See Operation During Reset.” Note: LOC is always cleared in external clock mode. 0 Clocks are operating normally 1 Clocks are not operating normally. Freescale Semiconductor — ...
Page 146
... Interrupt service not requested 1 Interrupt service request 7-12 Description Table 7-7). See Section 7.4.3, “System Clock Generation,” Module,” for details on how to configure the system clock mode during Table 7-7) Table 7-7. MCF5271 Reference Manual, Rev. 2 for details on how Chapter 10, Freescale Semiconductor ...
Page 147
... PLL clock mode. Whenever CLKMOD1 or CLKMOD0 is changed in reset, an immediate loss-of-lock condition occurs. Table 7-8 shows the clock-out frequency to clock-in frequency relationships for the possible system clock modes. Refer to Freescale Semiconductor Description CALPASS CALDONE Table 7-7 ...
Page 148
... MFD ( ) ∆F ± ref -------------------------------------------------------- - sys RFD × Section 7.1.3.3, “1:1 PLL Mode” sys/2 ref_1 Section 7.1.3.4, “External Clock Mode sys/2 ref (Bypass Mode)” Reset,” for more information. MCF5271 Reference Manual, Rev. 2 Cross-Reference and Section 7.1.3.2, Freescale Semiconductor ...
Page 149
... If frequency modulation is enabled (by writing to the EXP bit field), disable frequency modulation by writing 0x0 to the DEPTH field of the SYNCR programming the MFD, write the MFD value from step 1 to the SYNCR. If enabling frequency modulation, skip this step. Freescale Semiconductor Table 7-5 Reset,” for more information. NOTE Section 7.4.3, “ ...
Page 150
... Disable modulation by clearing the DEPTH field in the SYNCR. 3. Monitor LOCK bit. Do not proceed until the PLL is locked in non-modulation mode. 7-16 NOTE Section 7.4.5, “Frequency Modulation Depth Calibration.” for details )×M×P ) 2× MFD + 2 EXP = ------------------------------------------------------- - 100 MCF5271 Reference Manual, Rev. 2 The ⁄ mod ref Freescale Semiconductor ...
Page 151
... Finally, the error due to the manufacturing and environment variation alone can cause the frequency modulation depth error to be greater than 20 max F min Fmax = f Fmin = f Fmod = Fref/Q where Q = {40, 80} Figure 7-6. Frequency Modulation Waveform Freescale Semiconductor ∆Fm ∆Fm 1 ∆t = ----------- - F mod + {1%, 2%} sys/2 - {1%, 2%} sys/2 MCF5271 Reference Manual, Rev ...
Page 152
... EXP field of the SYNCR register resulting in an error count. The 7-18 and F ) remains within specification. Frequency modulation max min ( ( )×M×P 2× MFD + 2 EXP = ------------------------------------------------------- - 100 for a complete list of values to be used for the variable ( )×480×1 ) 100 ⁄ 2× 57.6 MCF5271 Reference Manual, Rev Freescale Semiconductor ...
Page 153
... CALPASS remains set. Figure 7-7 shows a block diagram of the calibration circuitry and its associated registers. Figure 7-8 shows a flow chart showing the steps taken by the calibration circuit. Reference Counter Control ICO Counter Figure 7-7. FM Auto-Calibration Data Flow Freescale Semiconductor Count 0 Expected (EXP A– ...
Page 154
... CAL0. Enable FM. N=7. CAL[ Allow system 3×384 reference counts to settle. Count M reference clock cycles. CALX = value in feedback counter. let DIFF=CALX-CAL0 NO DIFF>0 YES let ERR=DIFF-EXP YES CAL[N]=0 ERR> MCF5271 Reference Manual, Rev YES N=0? NO N=N-1 CALDONE=1 DONE PCALPASS=0 Freescale Semiconductor ...
Page 155
... Actual component values depend on crystal specifications. C1 VSSPLL ON-CHIP Figure 7-9. Crystal Oscillator Example The following subsections describe each major block of the PLL. Refer to these functional sub-blocks interact. Freescale Semiconductor 8-MHz Crystal Configuration ≥ 1 MΩ 470 Ω EXTAL XTAL ...
Page 156
... Lock LOCK Detect Loss of LOC Clock Detect Charge Pump up Charge PFD down Pump VDDPLL / VSSPLL MFD VDDI / VSSI MCF5271 Reference Manual, Rev Modulation Control ICO clkout Filter ICO Freescale Semiconductor ...
Page 157
... If the feedback counter has also counted N cycles, the process is repeated for counts. Then, if the two counters still match, the lock criteria is relaxed by one count and the system is notified that the PLL has achieved frequency lock. Freescale Semiconductor Table 7-9. ...
Page 158
... Set Relaxed Lock Condition and Notify System of Lock Condition Figure 7-11. Lock Detect Sequence MCF5271 Reference Manual, Rev. 2 Reference Count ≠ Feedback Count Count Reference Cycles and Compare Number of Feedback Cycles Elapsed Reference Count = Feedback Count = Same Count/Compare Sequence Freescale Semiconductor ...
Page 159
... To exit reset in PLL mode, the reference must be present, and the PLL must acquire lock. Reset initializes the clock module registers to a known startup state as described in “Memory Map/Register Definition.” Freescale Semiconductor Section 10.3.2, “Reset Status Register MCF5271 Reference Manual, Rev. 2 Functional Description Section 7 ...
Page 160
... None Expected PLL PLL Action MODE Action at During Stop Stop — — EXT Lose reference Stuck clock MCF5271 Reference Manual, Rev. 2 PLL Failure Alternate Clock Selected by LOC Circuit Until Reset PLL reference NA Figure 7-10. Comments Out — — — Freescale Semiconductor ...
Page 161
... Lose lock, f.b. clock, reference clock NRM Off On 0 Lose lock NRM Off On 1 Lose lock Freescale Semiconductor Expected PLL PLL Action MODE Action at During Stop Stop Regain NRM No regain Stuck Regain clocks, but SCM–> don’t regain lock unstable ...
Page 162
... Reset immediately ‘LK 1 ‘LC REF not entered during stop; SCM entered during stop only during oscillator startup — — — ‘LK 1 ‘LC REF mode not entered during stop — — — Wakeup without lock Freescale Semiconductor ...
Page 163
... NRM NRM Off X X Lose lock, f.b. clock, reference clock NRM Freescale Semiconductor Expected PLL PLL Action MODE Action at During Stop Stop Regain f.b. clock Unstable NRM No f.b. clock Stuck regain Lose reference SCM clock — — NRM Lose reference SCM clock Lose f ...
Page 164
... SCM Lose reference SCM clock MCF5271 Reference Manual, Rev. 2 Comments Out ‘LK 1 ‘LC — — — Reset immediately 0 0–>1 ‘ ‘LC ‘LK 1 ‘LC — — — Reset immediately — — — Wakeup without lock and Section 7.4.6.11, Freescale Semiconductor ...
Page 165
... LPICR. 3 The CCR is described in the Chip Configuration Module shown here only to warn against accidental writes to this register when accessing the LPCR. 8.2.1 Register Descriptions The following subsection describes the PM registers. Freescale Semiconductor [23:16] [15:8] Core Watchdog Low-Power 2 Control Register ...
Page 166
... SCM responds by asserting the request to exit low-power mode. 6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks. 7. With the processor clocks enabled, the core processes the pending interrupt request. 8-2 NOTE NOTE MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 167
... Low-Power Control Register (LPCR) The LPCR controls chip operation and module operation during low-power modes Reset 0 Address Figure 8-2. Low-Power Control Register (LPCR) Freescale Semiconductor XLPM_IPL[2: IPSBAR + 0x00_0012 Table 8-2. LPICR Field Description Description Table 8-3. XLPM_IPL Settings ...
Page 168
... Any type of reset • Any valid, enabled interrupt request Exiting from low power mode via an interrupt request requires: 8-4 Table 8-4. LPCR Field Descriptions Description LPMD[1: MCF5271 Reference Manual, Rev. 2 Mode STOP WAIT DOZE RUN Freescale Semiconductor ...
Page 169
... Stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation. The following subsections specify the operation of each module while in and when exiting low-power modes. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Functional Description 8-5 ...
Page 170
... The SDRAM self-refresh mode allows the SDRAM to enter a low-power state where internal refresh operations are used to maintain the integrity of the data stored in the SDRAM. 8-6 NOTE Section 8.3.2.4, “SDRAM MCF5271 Reference Manual, Rev. 2 Section 8.3.1, Freescale Semiconductor ...
Page 171
... C module is operable and may generate an interrupt to bring the device out of a low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller. The Freescale Semiconductor NOTE MCF5271 Reference Manual, Rev. 2 ...
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... CPU’s status register (SR). The interrupt must also be enabled in the interrupt controller’s interrupt mask register as well as at the module from which the interrupt request would originate. 8 resumes operation unless stop mode was exited by MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... When the CPU is inactive, a software reset cannot be generated to exit any low-power mode. 8.3.2.15 Chip Configuration Module The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode is exited by a reset, chip configuration may be executed if configured to do so. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Functional Description 8-9 ...
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... When not stopped, the PIT may generate an interrupt to exit the low-power modes. 8.3.2.20 BDM Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the CPU to exit any low-power mode. 8-10 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... UART0, UART1 and UART2 Module QSPI DMA Timers Interrupt controller Fast Ethernet Controller I/O Ports Reset Controller Chip Configuration Module Power Management Clock Module Edge port Watchdog timer Freescale Semiconductor Peripheral Status Wait Mode Doze Mode Stopped No Stopped Stopped No Stopped 3 Enabled Yes Enabled Enabled ...
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... Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect. 8-12 Peripheral Status Wait Mode Doze Mode 2 Enabled Yes Program 4 Enabled Yes Enabled Enabled No Enabled MCF5271 Reference Manual, Rev Wakeup Capability Stop Mode 2 Yes Stopped Yes Enabled Yes No Enabled No Freescale Semiconductor ...
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... Selects the chip operating mode • Selects external clock or phase-lock loop (PLL) mode with internal or external reference • Selects output pad drive strength • Selects boot device and data port size • Selects bus monitor configuration Freescale Semiconductor Reset Output Pad Configuration Strength Selection ...
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... Table 9-1. Signal Properties Function Reset configuration select 1 Clock mode select Reset configuration override pins for more information. Description”). The internal configuration signals MCF5271 Reference Manual, Rev. 2 Reset State Internal weak pull-up device — — Freescale Semiconductor ...
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... Table 9-3. Chip Configuration Module Memory Map IPSBAR Offset [31:24] 0x11_0004 Chip Configuration Register (CCR) 0x11_0008 Reset Configuration Register (RCON) 0x11_000C 0x11_0010 Freescale Semiconductor shows the accessibility of write-once bits. [23:16] [15:8] Low-Power Control Register (LPCR) Chip Identification Register (CIR) 3 Reserved 4 Unimplemented MCF5271 Reference Manual, Rev ...
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... TSIZ[1:0] function enabled. DMA Acknowlede function disabled on the TSIZ[1:0] pins. 9-4 for a description of the LPCR shown here only to warn against accidental NOTE SZEN PSTEN See Note IPSBAR + 0x11_0004 Table 9-4. CCR Field Descriptions Description shows the read/write accessibility of this write-once bit. MCF5271 Reference Manual, Rev BME BMT Freescale Semiconductor 0 ...
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... RCON values can only be overridden during reset configuration (see “Reset Configuration”) if the external RCON pin is asserted. RCON is a read-only register Reset Address Figure 9-3. Reset Configuration Register (RCON) Freescale Semiconductor Description shows the read/write accessibility of this write-once bit. shows the read/write accessibility of this write-once bit RCSC ...
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... This is the default value used for the MCF5271. BOOTPS[1: This is the default value used for the MCF5271. MCF5271 Reference Manual, Rev. 2 Chip Select Configuration PADDR[7:5] = A[23:21] PADDR[7] = CS6 PADDR[6:5] = A[22:21] PADDR[7:6] = CS[6:5] PADDR[5] = A[21] PADDR[7:5] = CS[6:4] Boot Port Size External 32 bits External 16 bits External 8 bits Freescale Semiconductor ...
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... Clock mode selections 6. Chip select configuration These functions are described here. 9.4.1 Reset Configuration During reset, the pins for the reset override functions are immediately configured to known states. Table 9-7 shows the states of the external pins while in reset. Freescale Semiconductor PIN ...
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... Internal weak pull-up device — Must be driven by external logic Table 9-8. 1 Function Chip Mode Selected 4 Master mode Reserved Boot Device External with 32-bit port External with 8-bit port External with 16-bit port Output Pad Drive Strength 4 Partial strength Full strength Freescale Semiconductor ...
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... Section 9.3.3.2, “Reset Configuration Register (RCON).” MCF5271, there is only one valid chip mode setting. Table 9-9. Chip Configuration Mode Selection During reset, certain module configurations depend on whether emulation mode is active as determined by the state of the internal emulation signal. Freescale Semiconductor Default Override Pins 2,3 Configuration ...
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... Once out of reset, the CLKMOD pins have no effect on the clock mode selection. 9-10 Table 9-11. Clock Mode Selection CLKMOD[1] CLKMOD[ MCF5271 Reference Manual, Rev. 2 Table 9-10. Once reset 1 RCON[RLOAD] D21 driven low D21 driven high Table 9-11 summarizes 1 PLL SYNSR Bits PLLMODE PLLSEL PLLREF Freescale Semiconductor ...
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... Reset Reset initializes CCM registers to a known startup state as described in Map/Register Definition.” Section 9.4, “Functional Description.” Freescale Semiconductor The CCM controls chip configuration at reset as described in MCF5271 Reference Manual, Rev. 2 Reset Table 9-8 shows Section 9.3, “Memory ...
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... Chip Configuration Module (CCM) 9-12 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... Watchdog timer — Phase locked-loop (PLL) loss of lock — PLL loss of clock — Software • Software-assertable RESET pin independent of chip reset state • Software-readable status flags indicating the cause of the last reset Freescale Semiconductor RESET Pin Reset Controller MCF5271 Reference Manual, Rev. 2 ...
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... Reset Control Register (RCR) The RCR allows software control for requesting a reset and for independently asserting the external RSTOUT pin. 10-2 Input Direction Hysteresis — [23:16] [15:8] 2 RSR Reserved MCF5271 Reference Manual, Rev. 2 Input Synchronization 1 Y — 1 [7:0] Access 2 Reserved S/U Freescale Semiconductor ...
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... The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset condition. RSR can be read at any time. Writing to RSR has no effect Reset 0 Address Figure 10-3. Reset Status Register (RSR) Freescale Semiconductor IPSBAR + 0x11_0000 Table 10-3. RCR Field Descriptions ...
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... External RESET pin (not stop mode) External RESET pin (during stop mode) Watchdog timer Loss of clock Loss of lock Software 10-4 Table 10-4. RSR Field Descriptions Description Table 10-5. Reset Source Summary Source Asynchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Synchronous MCF5271 Reference Manual, Rev. 2 Type Freescale Semiconductor ...
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... Loss-of-Clock Reset This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and either the PLL reference or the PLL itself fails. The reset controller asserts RSTOUT for Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Functional Description DD ...
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... The reset logic control flow is shown in been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. 10-6 Figure 10-4. In this figure, the control state boxes have MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... LOSS OF CLOCK LOSS OF LOCK? N RESET 3 PIN OR WD TIMEOUT OR SW RESET NEGATE RSTOUT Freescale Semiconductor ENABLE BUS MONITOR Y 6 BUS CYCLE COMPLETE ASSERT RSTOUT AND LATCH RESET STATUS 8 RESET NEGATED PLL MODE WAIT 512 CLKOUT CYCLES 11 RCON ASSERTED? N Figure 10-4. Reset Control Flow MCF5271 Reference Manual, Rev ...
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... If the external RESET pin is asserted for at least four rising CLKOUT edges while waiting for PLL lock or the 512 cycles, the external reset is recognized. Reset processing switches to wait for the external RESET pin to negate (8). 10-8 Figure 10-4. MCF5271 Reference Manual, Rev. 2 Figure 10-4. All cycle Freescale Semiconductor ...
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... EXT, SOFT, and/or WDR bits are set. If the RSR bits are latched (4) during the internal reset sequence with the RESET pin not asserted and no SOFT or WDR event, then the LOC and/or LOL bits are the only bits set. Freescale Semiconductor MCF5271 Reference Manual, Rev. 2 Functional Description ...
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... Reset Controller Module 10-10 MCF5271 Reference Manual, Rev. 2 Freescale Semiconductor ...
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... Please note that the core watchdog timer is unable to reset the device only permitted to assert an interrupt. For resetting the device, use the second watchdog timer. 11.1.2 Features The SCM includes these distinctive features: Freescale Semiconductor NOTE Chapter 20, “Watchdog Timer MCF5271 Reference Manual, Rev. 2 Module” for more ...
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... IPSBAR — RAMBAR — CRSR CWCR LPICR 2 DMAREQC — MPARK MPR PACR0 PACR1 PACR2 PACR4 — PACR5 PACR7 — PACR8 MCF5271 Reference Manual, Rev. 2 11-1. All the registers in the SCM are [15:8] [7:0] 1 CWSR — PACR3 PACR6 — Freescale Semiconductor ...