MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 363

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.2.4.10 Transmit Control Register (TCR)
The TCR is read/write and is written by the user to configure the transmit block. This register is
cleared at system reset. Bits 2 and 1 should be modified only when ECR[ETHER_EN] = 0.
Freescale Semiconductor
Address
Reset
Reset
31–5
Bits
W
W
R
R
4
3
2
1
0
31
15
0
0
0
0
TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is
RFC_PAUS
30
14
0
0
0
0
Name
FDEN
HBC
GTS
—
E
29
13
0
0
0
0
Figure 19-11. Transmit Control Register (TCR)
Reserved, should be cleared.
Receive frame control pause. This read-only status bit will be asserted when a full duplex
flow control pause frame has been received and the transmitter is paused for the duration
defined in this pause frame. This bit will automatically clear when the pause duration is
complete.
set, the MAC will stop transmission of data frames after the current transmission is
complete. At this time, the GRA interrupt in the EIR register will be asserted. With
transmission of data frames stopped, the MAC will transmit a MAC Control PAUSE frame.
Next, the MAC will clear the TFC_PAUSE bit and resume transmitting data frames. Note
that if the transmitter is paused due to user assertion of GTS or reception of a PAUSE
frame, the MAC may still transmit a MAC Control PAUSE frame.
Full duplex enable. If set, frames are transmitted independent of carrier sense and
collision inputs. This bit should only be modified when ETHER_EN is deasserted.
Heartbeat control. If set, the heartbeat check is performed following end of transmission
and the HB bit in the status register will be set if the collision input does not assert within
the heartbeat window. This bit should only be modified when ETHER_EN is deasserted.
Graceful transmit stop. When this bit is set, the MAC will stop transmission after any frame
that is currently being transmitted is complete and the GRA interrupt in the EIR register
will be asserted. If frame transmission is not currently underway, the GRA interrupt will be
asserted immediately. Once transmission has completed, a “restart” can be accomplished
by clearing the GTS bit. The next frame in the transmit FIFO will then be transmitted. If an
early collision occurs during transmission when GTS = 1, transmission will stop after the
collision. The frame will be transmitted again once GTS is cleared. Note that there may be
old frames in the transmit FIFO that will be transmitted when GTS is reasserted. To avoid
this deassert ECR[ETHER_EN] following the GRA interrupt.
28
12
0
0
0
0
Table 19-14. TCR Field Descriptions
27
11
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
0
0
25
0
0
0
0
9
IPSBAR + 0x10C4
24
0
0
0
0
8
23
0
0
7
0
0
Description
22
0
0
0
0
6
21
0
0
5
0
0
PAUSE
RFC_
20
0
0
0
4
PAUSE
Memory Map/Register Definition
TFC_
19
0
0
0
3
FEDN HBC GTS
18
0
0
2
0
17
0
0
0
1
16
0
0
0
0
19-19