MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 360

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.2.4.7 MII Speed Control Register (MSCR)
The MSCR provides control of the MII clock (EMDC pin) frequency and allows a preamble drop
on the MII management frame.
The MII_SPEED field must be programmed with a value to provide an EMDC frequency of less
than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED
must be set to a non-zero value in order to source a read or write management frame. After the
management frame is complete the MSCR register may optionally be set to zero to turn off the
EMDC. The EMDC generated will have a 50% duty cycle except when MII_SPEED is changed
during operation (change will take effect following either a rising or falling edge of EMDC).
If the system clock is 75 MHz, programming MII_SPEED to 0x0F will result in an EMDC
frequency of 75 MHz / (15 × 2) = 2.5 MHz. A table showing optimum values for MII_SPEED as
a function of system clock frequency is provided below.
19-16
Address
Reset
Reset
31–8
Bits
6–1
7
0
W
W
R
R
31
15
0
0
0
0
MII_SPEED MII_SPEED controls the frequency of the MII management interface clock (EMDC)
DIS_PRE
Name
30
14
0
0
0
0
—
—
Figure 19-8. MII Speed Control Register (MSCR)
29
13
0
0
0
0
Reserved, should be cleared.
Asserting this bit will cause preamble (32 1’s) not to be prepended to the MII management
frame. The MII standard allows the preamble to be dropped if the attached PHY device(s)
does not require it.
relative to the system clock. A value of 0 in this field will “turn off” the EMDC and leave it
in low voltage state. Any non-zero value will result in the EMDC frequency of
1/(MII_SPEED × 2) of the system clock frequency.
Reserved, should be cleared.
28
12
Table 19-10. MSCR Field Descriptions
0
0
0
0
27
11
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
0
0
25
0
0
0
0
9
IPSBAR + 0x1044
24
0
0
0
0
8
DIS_
PRE
23
0
0
0
7
Description
22
0
0
6
0
21
0
0
0
5
MII_SPEED
20
0
0
0
4
19
0
0
0
3
Freescale Semiconductor
18
0
0
0
2
17
0
0
0
1
16
0
0
0
0
0