MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 449

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Bits
6–4
3–2
Value
000
001
010
100
101
011
110
111
00
01
10
11
NO COMMAND
RESET MODE
REGISTER POINTER
RESET RECEIVER
RESET TRANSMITTER
RESET ERROR
STATUS
RESET BREAK
CHANGE INTERRUPT
START BREAK
STOP BREAK
NO ACTION TAKEN
TRANSMITTER
ENABLE
TRANSMITTER
DISABLE
Command
—
–
Table 24-7. UCRn Field Descriptions
—
Causes the mode register pointer to point to UMR1n.
Immediately disables the receiver, clears USRn[FFULL,RxRDY], and reinitializes
the receiver FIFO pointer. No other registers are altered. Because it places the
receiver in a known state, use this command instead of
reconfiguring the receiver.
Immediately disables the transmitter and clears USRn[TxEMP,TxRDY]. No other
registers are altered. Because it places the transmitter in a known state, use this
command instead of
Clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after
a data block is received.
Clears the delta break bit, UISRn[DB].
Forces UnTXD low. If the transmitter is empty, the break may be delayed up to one
bit time. If the transmitter is active, the break starts when character transmission
completes. The break is delayed until any character in the transmitter shift register
is sent. Any character in the transmitter holding register is sent after the break. The
transmitter must be enabled for the command to be accepted. This command
ignores the state of UnCTS.
Causes UnTXD to go high (mark) within two bit times. Any characters in the
transmit buffer are sent.
Causes the transmitter to stay in its current mode: if the transmitter is enabled, it
remains enabled; if the transmitter is disabled, it remains disabled.
Enables operation of the channel’s transmitter. USRn[TxEMP,TxRDY] are set. If
the transmitter is already enabled, this command has no effect.
Terminates transmitter operation and clears USRn[TxEMP,TxRDY]. If a character
is being sent when the transmitter is disabled, transmission completes before the
transmitter becomes inactive. If the transmitter is already disabled, the command
has no effect.
Reserved, do not use.
MISC Field (This field selects a single command.)
TC Field (This field selects a single command)
MCF5271 Reference Manual, Rev. 2
TRANSMITTER DISABLE
Description
when reconfiguring the transmitter.
Memory Map/Register Definition
RECEIVER DISABLE
when
24-11