MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 186

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chip Configuration Module (CCM)
9.4.3
During reset configuration, the CS0 chip select pin is configured to select an external boot device.
In this case, the V (valid) bit in the CSMR0 register is ignored, and CS0 is enabled after reset. CS0
is asserted for the initial boot fetch accessed from address 0x0000_0000 for the Stack Pointer and
address 0x0000_0004 for the program counter (PC). It is assumed that the reset vector loaded from
address 0x0000_0004 causes the CPU to start executing from external memory space decoded by
CS0.
9.4.4
Output pad strength is determined during reset configuration as shown in
is exited, the output pad strength configuration can be changed by programming the LOAD bit of
the chip configuration register.
9.4.5
The clock mode is selected during reset and reflected in the PLLMODE, PLLSEL, and PLLREF
bits of SYNSR. Once reset is exited, the clock mode cannot be changed.
clock mode selection during reset configuration.
9-10
1
External clock mode; PLL disabled
1:1 PLL mode
Normal PLL mode; external clock reference
Normal PLL mode; crystal oscillator reference
There is no default configuration for clock mode selection. The actual values for the CLKMOD pins must always be driven
during reset. Once out of reset, the CLKMOD pins have no effect on the clock mode selection.
Boot Device Selection
Output Pad Strength Configuration
Clock Mode Selection
1
Output pads configured for partial strength
Output pads configured for full strength
Clock Mode
Modifying the default configurations is possible only if the external RCON pin is asserted low.
Optional Pin Function Selection
Table 9-10. Output Pad Driver Strength Selection
Table 9-11. Clock Mode Selection
MCF5271 Reference Manual, Rev. 2
CLKMOD[1] CLKMOD[0]
0
0
1
1
0
1
0
0
PLLMODE
RCON[RLOAD]
D21 driven high
D21 driven low
1
0
1
1
1
PLL SYNSR Bits
Table 9-11
Table
1
PLLSEL
Freescale Semiconductor
0
0
1
1
9-10. Once reset
summarizes
PLLREF
0
0
0
1