MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 349

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Memory Map/Register Definition
software via the serial management interface (EMDC/EMDIO pins) to the transceiver. Refer to the
MMFR and MSCR register descriptions as well as the section on the MII for a description of how
to read and write registers in the transceiver via this interface.
19.1.5.2 10 Mpbs 7-Wire Interface Operation
The FEC supports a 7-wire interface as used by many 10 Mbps ethernet transceivers. The
RCR[MII_MODE] bit controls this functionality. If this bit is cleared, the MII mode is disabled
and the 10 Mbps, 7-wire mode is enabled.
19.1.6 Address Recognition Options
The address options supported are promiscuous, broadcast reject, individual address (hash or exact
match), and multicast hash match. Address recognition options are discussed in detail in
Section 19.3.8, “Ethernet Address
Recognition.”
19.1.7 Internal Loopback
Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in
Section 19.3.13, “ Internal and External
Loopback.”
19.2
Memory Map/Register Definition
This section gives an overview of the registers, followed by a description of the buffers.
The FEC is programmed by a combination of control/status registers (CSRs) and buffer
descriptors. The CSRs are used for mode control and to extract global status information. The
descriptors are used to pass data buffers and related buffer information between the hardware and
software.
19.2.1 High-Level Module Memory Map
The FEC implementation requires a 1-Kbyte memory map space. This is divided into 2 sections
of 512 bytes each. The first is used for control/status registers. The second contains event/statistic
counters held in the MIB block.
Table 19-1
defines the top level memory map.
Table 19-1. Module Memory Map
Address
Function
IPSBAR + 0x1000–11FF
Control/Status Registers
IPSBAR + 0x1200–13FF
MIB Block Counters
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
19-5