MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 268
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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DMA Controller Module
14.2
The DMA module can move data within system memory (including memory and peripheral
devices) with minimal processor intervention, greatly improving overall system performance. The
DMA module consists of four independent, functionally equivalent channels, so references to
DMA in this chapter apply to any of the channels. It is not possible to implicitly address all four
channels at once.
The processor generates DMA requests internally by setting DCR[START]; the UART modules
and DMA timers can generate a DMA request by asserting internal DREQ signals. The processor
can program bus bandwidth for each channel. The channels support cycle-steal and continuous
transfer modes; see
The DMA controller supports dual-address transfers. The DMA channels support up to 32 data
bits.
14-4
• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
• Continuous-mode or cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
• Modulo addressing on source and destination addresses
• Automatic channel linking
• Dual-address transfers—A dual-address transfer consists of a read followed by a write and
is initiated by an internal request using the START bit or by asserting DREQn. Two types
of transfer can occur: a read from a source device or a write to a destination device. See
Figure 14-2
DMA Transfer Overview
for more information.
Section 14.4.1, “Transfer Requests (Cycle-Steal and Continuous
Figure 14-2. Dual-Address Transfer
DMA
DMA
MCF5271 Reference Manual, Rev. 2
Control and Data
Control and Data
Peripheral
Peripheral
Memory/
Memory/
Freescale Semiconductor
Modes).”
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