MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 459

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

24.4.2.2 Receiver
The receiver is enabled through its UCRn, as described in
Registers
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on UnRXD, the
state of UnRXD is sampled eight times on the edge of the bit time clock starting one-half clock
after the transition (asynchronous operation) or at the next rising edge of the bit time clock
(synchronous operation). If UnRXD is sampled high, the start bit is invalid and the search for the
valid start bit begins again.
If UnRXD is still low, a valid start bit is assumed and the receiver continues sampling the input at
one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and
parity, if any, is assembled and one stop bit is detected. Data on the UnRXD input is sampled on
the rising edge of the programmed clock source. The lsb is received first. The data is then
transferred to a receiver holding register and USRn[RxRDY] is set. If the character is less than
eight bits, the most significant unused bits in the receiver holding register are cleared.
Freescale Semiconductor
USRn[TxRDY]
Transmitter
UnCTS
Enabled
UnRTS
UnTXD
internal
module
1
2
3
4
UMR2n[TxRTS] = 1
select
Cn = transmit characters
W = write
UMR2n[TxCTS] = 1
(UCRn).”
3
4
Manually asserted
by
C1
W
BIT
2
1
Figure 24-19. Transmitter Timing Diagram
-
SET
C1
1
command
C1 in transmission
C2
W
MCF5271 Reference Manual, Rev. 2
C2
C3
W
break
Start
W
C3
Break
Section 24.3.5, “UART Command
C4 Stop
W
break
W
transmitted
C4
not
C5
W
Functional Description
Manually
asserted
C6
W
C6
24-21