MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 402

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Programmable Interrupt Timer Modules (PIT0–PIT3)
21.1.3 Low-Power Mode Operation
This subsection describes the operation of the PIT modules in low-power modes and debug mode
of operation. Low-power modes are described in the Power Management Module.
shows the PIT module operation in low-power modes, and how it can exit from each mode.
In wait mode, the PIT module continues to operate as in run mode and can be configured to exit
the low-power mode by generating an interrupt request. In doze mode with the PCSRn[DOZE] bit
set, PIT module operation stops. In doze mode with the PCSRn[DOZE] bit cleared, doze mode
does not affect PIT operation. When doze mode is exited, the PIT continues to operate in the state
it was in prior to doze mode. In stop mode, the system clock is absent, and PIT module operation
stops.
In debug mode with the PCSRn[DBG] bit set, PIT module operation stops. In debug mode with
the PCSRn[DBG] bit cleared, debug mode does not affect PIT operation. When debug mode is
exited, the PIT continues to operate in its pre-debug mode state, but any updates made in debug
mode remain.
21.2
This section contains a memory map, shown in
PIT0–PIT3.
21-2
IPSBAR Offset
Low-power Mode
0x15_0000
0x15_0004
Memory Map/Register Definition
Debug
Table 21-2. Programmable Interrupt Timer Modules Memory Map
Doze
The low-power interrupt control register (LPICR) in the System
Control Module specifies the interrupt level at or above which the
device can be brought out of a low-power mode.
Wait
Stop
Table 21-1. PIT Module Operation in Low-power Modes
PIT Control and Status Register
PIT Count Register (PCNTR0)
[31:24]
Normal if PCSRn[DOZE] cleared,
Normal if PCSRn[DBG] cleared,
(PCSR0)
stopped otherwise
stopped otherwise
MCF5271 Reference Manual, Rev. 2
PIT Operation
Stopped
Normal
[23:16]
NOTE
Table
21-2, and describes the register structure for
PIT Modulus Register (PMR0)
N/A
Any IRQn Interrupt at or above level in LPICR
No
No. Any IRQn Interrupt will be serviced upon
[15:8]
normal exit from debug mode
Reserved
Mode Exit
2
[7:0]
Freescale Semiconductor
Access
S/U
S
Table 21-1
1