MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 105
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.4.1.1
This section describes behavior when the fractional mode is used (MACSR[F/I] is set).
4.4.1.1.1
When the processor is in fractional mode, there are two operations during which rounding can
occur.
To understand the round-to-nearest-even method, consider the following example involving the
rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is
rounded to the closest 16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and
the low-order 16 bits be R0.L.
Freescale Semiconductor
• Execution of a store accumulator instruction (MOV.L ACCx,Rx). The lsbs of the 48-bit
• Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero,
• If R0.L is less than 0x8000, the result is truncated to the value of R0.U.
• If R0.L is greater than 0x8000, the upper word is incremented (rounded up).
• If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is
accumulator logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] is
cleared, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U]
is set, the low-order 24 bits are used to round the resulting 16-bit fraction.
multiplying two 32-bit numbers creates a 64-bit product that is truncated to the upper 40
bits; otherwise, it is rounded using round-to-nearest (even) method.
based on the lsb of R0.U, so the result is always even (lsb = 0).
— If the lsb of R0.U = 1 and R0.L = 0x8000, the number is rounded up.
Fractional Operation Mode
Rounding
Table 4-2. Summary of S/U, F/I, and R/T Control Bits
S/U F/I R/T
0
0
0
1
1
1
0
1
1
0
1
1
MCF5271 Reference Manual, Rev. 2
x
0
1
x
0
1
Signed, integer
Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-32-bits on accumulator stores
Unsigned, integer
Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Operational Modes
Memory Map/Register Definition
4-9
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