MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 271

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

14.3.2 Source Address Registers (SAR0–SAR3)
SARn, shown in
Freescale Semiconductor
Address
Reset
Reset
15–0
Bits
W
W
R
R
31
15
0
0
The backdoor enable bit must be set in the SCM RAMBAR as well as
the secondary port valid bit in the Core RAMBAR in order to enable
backdoor accesses from the DMA to SRAM. See
“Memory Base Address Register
“SRAM Base Address Register
DMACn
Name
Figure
30
14
0
0
Table 14-2. DMAREQC Field Description (Continued)
29
13
0
0
Figure 14-4. Source Address Registers (SARn)
14-4, contains the address from which the DMA controller requests data.
DMA channel n. Each four bit field defines the logical connection between the DMA
requestors and that DMA channel.There are ten possible requesters (4 DMA Timers and
6 UARTs). Any request can be routed to any of the DMA channels. Effectively, the
DMAREQC provides a software-controlled routing matrix of the 10 DMA request signals to
the 4 channels of the DMA module. DMAC3 controls DMA channel 3, DMAC2 controls
DMA channel 2, etc.
0100 DMA Timer 0.
0101 DMA Timer 1.
0110 DMA Timer 2.
0111 DMA Timer 3.
1000 UART0 Receive.
1001 UART1 Receive.
1010 UART2 Receive.
1100 UART0 Transmit.
1101 UART1 Transmit.
1110 UART2 Transmit.
All other values are reserved and will not generate a DMA request.
28
12
IPSBAR + 0x00_0100 (DMA0); IPSBAR + 0x00_0110 (DMA1);
0
0
IPSBAR + 0x00_0120 (DMA2); IPSBAR + 0x00_0130 (DMA3)
27
11
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
25
0
0
9
NOTE
(RAMBAR)” for more details.
24
0
0
8
(RAMBAR)” and
SAR
SAR
23
Description
0
0
7
22
0
6
0
21
0
0
5
Section 11.2.1.2,
Section 6.2.1,
20
0
0
4
Memory Map/Register Definition
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
14-7