MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 117

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 5
Cache
5.1
This chapter describes the MCF5271 cache operation.
5.1.1
5.1.2
The cache is a direct-mapped single-cycle memory. It may be configured as an instruction cache,
a write-through data cache, or a split instruction/data cache. The cache storage is organized as 512
lines, each containing 16 bytes. The memory storage consists of a 512-entry tag array (containing
addresses and a valid bit), and a data array containing 8 Kbytes, organized as 2048 × 32 bits.
Cache configuration is controlled by bits in the cache control register (CACR) that is detailed later
in this chapter. For the instruction or data-only configurations, only the associated instruction or
data line-fill buffer is used. For the split cache configuration, one-half of the tag and storage arrays
is used for an instruction cache and one-half is used for a data cache. The split cache configuration
uses both the instruction and the data line-fill buffers. The core’s local bus is a unified bus used for
both instruction and data fetches. Therefore, the cache can have only one fetch, either instruction
or data, active at one time.
For the instruction- or data-only configurations, the cache tag and storage arrays are accessed in
parallel: fetch address bits [12:4] addressing the tag array and fetch address bits [12:2] addressing
the storage array. For the split cache configuration, the cache tag and storage arrays are accessed
in parallel. The msb of the tag array address is set for instruction fetches and cleared for operand
fetches; fetch address bits [11:4] provide the rest of the tag array address. The tag array outputs the
address mapped to the given cache location along with the valid bit for the line. This address field
is compared to bits [31:13] for instruction- or data-only configurations and to bits [31:12] for a
split configuration of the fetch address from the local bus to determine if a cache hit has occurred.
Freescale Semiconductor
• Configurable as instruction, data, or split instruction/data cache
• 8-Kbyte direct-mapped cache
• Single-cycle access on cache hits
• Physically located on the Coldfire core's high-speed local bus
• Nonblocking design to maximize performance
• Separate instruction and data 16-Byte line-fill buffers
• Configurable instruction cache miss-fetch algorithm
Introduction
Features
Physical Organization
MCF5271 Reference Manual, Rev. 2
5-1