MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 463

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Features of this local loop-back mode are as follows:
24.4.3.3 Remote Loop-Back Mode
In remote loop-back mode, shown in
data bit by bit on the UnTXD output. The local CPU-to-transmitter link is disabled. This mode is
useful in testing receiver and transmitter operation of a remote channel. For this mode, the
transmitter uses the receiver clock.
Because the receiver is not active, received data cannot be read by the CPU and all status
conditions are inactive. Received parity is not checked and is not recalculated for transmission.
Stop bits are sent as they are received. A received break is echoed as received until the next valid
start bit is detected.
24.4.4
Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or
multiprocessor applications. In this mode, a master can transmit an address character followed by
a block of data characters targeted for one of up to 256 slave stations.
Although slave stations have their channel receivers disabled, they continuously monitor the
master’s data stream. When the master sends an address character, the slave receiver channel
notifies its respective CPU by setting USRn[RxRDY] and generating an interrupt (if programmed
to do so). Each slave station CPU then compares the received address to its station address and
enables its receiver if it wishes to receive the subsequent data characters or block of data from the
Freescale Semiconductor
• Transmitter and CPU-to-receiver communications continue normally in this mode.
• UnRXD input data is ignored
• UnTXD is held marking
• The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the
receiver need not be.
Multidrop Mode
CPU
CPU
Disabled
Disabled
Figure 24-23. Remote Loop-Back
Figure 24-22. Local Loop-Back
MCF5271 Reference Manual, Rev. 2
Figure
Rx
Tx
Rx
Tx
24-23, the channel automatically transmits received
Disabled
Disabled
Disabled
Disabled
UnRXD Input
UnTXD Output
UnRXD Input
UnTXD Input
Functional Description
24-25