MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 95

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

FF1
Operation:
Assembler Syntax:
Attributes:
The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and ending
with the least-significant bit (Dx[0]), searching for the first set bit. The data register is then loaded
with the offset count from bit 31 where the first set bit appears, as shown below. If the source
data is zero, then an offset of 32 is returned.
Instruction Field:
Freescale Semiconductor
Condition
Codes:
•
Instruction
Format:
Destination Register field—Specifies the destination data register, Dx.
Opcode present
—
X
FF1
15
0
N
∗
14
0
FF1.L Dx
Bit Offset of the First Logical One in Register → Destination
Size = longword
Z
∗
13
0
Find First One in Register
(Supported Starting with ISA A+)
0b00000 . . . 0010
0b00000 . . . 0001
0b00000 . . . 0000
12
V
0
0
0b001-- . . . ----
0b01--- . . . ----
MCF5271 Reference Manual, Rev. 2
0b1---- . . . ----
Old Dx[31:0]
V2, V3 Core (ISA_A)
11
0
...
C
0
No
10
1
X Not affected
N Set if the msb of the source operand is set; cleared
Z Set if the source operand is zero; cleared otherwise
V Always cleared
C Always cleared
0
9
otherwise
New Dx[31:0]
0
8
0x0000 0000
0x0000 0001
0x0000 0002
0x0000 001E
0x0000 001F
0x0000 0020
V4 Core (ISA_B)
...
1
7
ColdFire Instruction Set Architecture Enhancements
No
1
6
5
0
4
0
V2 Core (ISA_A+)
3
0
Yes
2
Register, Dx
FF1
Destination
1
0
3-29