MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 64

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Signal Descriptions
2.3.13 Test Signals
Table 2-15
2-14
Development Serial
Output
Debug Data
Processor Status
Outputs
Processor Status Clock PSTCLK
Signal Name
describes test signals.
DSO
DDATA[3:0]
PST[3:0]
Table 2-13. Debug Support Signals (Continued)
Abbreviation
PST[3:0]
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
1011
1100
1101
0111
1110
1111
Table 2-14. Processor Status
Continue execution
Begin execution of one instruction
Reserved
Entry into user mode
Begin execution of PULSE and WDDATA instructions
Begin execution of taken branch
Reserved
Begin execution of RTE instruction
Begin one-byte transfer on DDATA
Begin two-byte transfer on DDATA
Begin three-byte transfer on DDATA
Begin four-byte transfer on DDATA
Exception processing
Reserved
Processor is stopped
Processor is halted
MCF5271 Reference Manual, Rev. 2
This internally-registered signal provides serial output
communication for BDM module responses.
Display captured processor data and breakpoint status. The PSTCLK
signal can be used by the development system to know when to
sample DDATA[3:0].
Indicate core status, as shown in
synchronous with the processor clock; status is unrelated to the
current bus transfer. The PSTCLK signal can be used by the
development system to know when to sample PST[3:0].
PSTCLK indicates when the development system should sample
PST and DDATA values.
Processor Status
Function
Table
2-14. Debug mode timing is
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I/O
O
O
O
O