MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 296

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chip Select Module
Each CSCR, shown in
activation of each chip select.
16.3.2.1 External Boot Chip Select Operation
CS0, the external boot chip select, allows address decoding for boot ROM before system
initialization. Its operation differs from other external chip select outputs after system reset.
After system reset, CS0 is asserted for every external access. No other chip select can be used until
the valid bit, CSMR0[V], is set, at which point CS0 functions as configured and CS[7:1] can be
used. At reset, the port size function of the external boot chip select is determined by the logic
levels of the inputs on D[20:19].
configuration signals multiplexed with D[20:19].
Provided the required address range is in the chip select address register (CSAR0), CS0 can be
programmed to continue decoding for a range of addresses after the CSMR0[V] is set, after which
the external boot chip select can be restored only by a system reset.
16.4 Memory Map/Register Definition
Table 16-4
16-6
0x00_008C
0x00_009C
0x00_0080
0x00_0084
0x00_0088
0x00_0090
0x00_0094
0x00_0098
IPSBAR
Offset
shows the chip select register memory map. Reading reserved locations returns zeros.
Chip select address register—bank 0 (CSAR0)
Chip select address register—bank 1 (CSAR1)
Chip select address register—bank 2 (CSAR2)
Table 16-3. D[20:19] External Boot Chip Select Configuration
[31:24]
Figure
D[20:19]
Reserved
Reserved
16-6, controls the auto-acknowledge, port size, burst capability, and
Table 16-4. Chip Select Registers
00
01
10
11
Table 16-3
MCF5271 Reference Manual, Rev. 2
Chip select mask register—bank 0 (CSMR0)
1
Chip select mask register—bank 1 (CSMR1)
1
Chip select mask register—bank 2 (CSMR2)
[23:16]
and
Boot Device/Data Port Size
Table 16-3
External (32-bit)
External (16-bit)
External (32-bit)
External (8-bit)
Chip select control register—bank 0 (CSCR0)
Chip select control register—bank 1 (CSCR1)
list the various reset encodings for the
[15:8]
Reserved
Reserved
Reserved
1
1
1
Freescale Semiconductor
[7:0]